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I have a doubt regarding the AXI3/4 protocol. Assume a hypothetical scenario where a single master issues a valid Read and Write transaction to the same address simultaneously.

  1. From the AXI specification, I understand that there is no interdependence between reads and writes and each has a channel of its own. With this in mind, is the above scenario valid?

  2. In case the above scenario is valid, is there a specific order in which these requests are served? (so that there is determinism in the type of response to expect from the master, since there are two ways this could end)

I am aware that (2) can depend on a lot of factors related to the master (posted writes, wait for response read, instruction execution for read after write etc.) and that AXI offers semaphore mechanisms through Exclusive Accesses. But these aside, what should be the expected behaviour?

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If the transaction is indicated as "non-modifiable," and both the Read and Write commands use the same ARID/AWID, the order must be preserved. This doesn't cover the case of simultaneous Read and Write commands, which is certainly possible for AXI.

Here's some additional info I found in section A4.3.2 of the AXI Spec (ARM document IHI 0022F.b). My answer is an interpretation of this excerpt:

Ordering between the independent read and write channels can only be guaranteed if a transaction in one direction is issued only after any earlier transaction in the other direction has received a response. If a transaction in one direction is issued before receiving the response to any earlier transaction in the other direction, then no ordering exists between the transactions.

If both transactions arrive at the AXI slave simultaneously, the behavior depends on the slave. For a dual-port RAM, you could conceivably read while writing to the same address. The Read result would then depend on the dual-port RAM controller. For something like DDR3 which can't have simultaneous R/W, the ordering behavior depends on the R/W priority in the controller, again.

Later in section A6.1, this is confirmed even more explicitly:

Read and write address channels are independent and in this specification, are defined to be in different directions. If an ordering relationship is required between two transactions with the same ID that are in different directions, then a master must wait to receive a response to the first transaction before issuing the second transaction.

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  • \$\begingroup\$ That excerpt from the specification was one of the reasons I had this doubt/confusion. This statement " If a transaction in one direction is issued before receiving the response to any earlier transaction in the other direction, then no ordering exists between the transactions." essentially introduces non-determinism on the expected behavior in the sense that a master no longer knows if it has read the old value or the updated value. \$\endgroup\$ – Rajesh S Apr 30 at 15:27
  • \$\begingroup\$ I agree with the slave dependency or even latency affecting which one is served first, that was the reason I mentioned hypothetical, the protocol aspect still seems unclear to me. After all the protocol should be independent of master/slave conditions is my understanding. \$\endgroup\$ – Rajesh S Apr 30 at 15:28
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    \$\begingroup\$ @RajeshS "the protocol should be independent of master/slave conditions" maybe it should be, but it isn't. There are so many edge cases, that I think if the protocol forced a certain behavior on all AXI devices, then it would be a detriment. In this case, the master should either be aware of the slave behavior (assuming there are no interconnects in the way), or understand the consequences of R/W collisions. This is not a problem unique to AXI. \$\endgroup\$ – Kevin Kruse Apr 30 at 15:36
  • \$\begingroup\$ Could you please mention the version of specification you are referring to? In the one which I am referring to, this is worded slightly differently although the meaning remains the same. "Because the read and write address channels are independent, if an ordering relationship is required between two transactions with the same ID that are in different directions, then a master must wait to receive a response to the first transaction before issuing the second transaction." \$\endgroup\$ – Rajesh S Apr 30 at 15:44

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