I have been designing some two input XOR-XNOR circuits using Cadence Virtuoso. All of them are working as expected but there is a little problem when both the inputs make a transition; the XOR and XNOR outputs encounter a peak. Consider one of those circuits shown below.
So when A goes from 0 to 1 and B goes from 1 to 0, both XOR and XNOR encounter a dip and a peak respectively, which should not be the case. I am not able to understand why this is happening. I think that it is due to some delays in the MOS, but that reasoning is not sufficient. Any help is appreciated.