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I have been designing some two input XOR-XNOR circuits using Cadence Virtuoso. All of them are working as expected but there is a little problem when both the inputs make a transition; the XOR and XNOR outputs encounter a peak. Consider one of those circuits shown below.

enter image description here

The XOR and XNOR pins have been already marked. The output is shown below. enter image description here

So when A goes from 0 to 1 and B goes from 1 to 0, both XOR and XNOR encounter a dip and a peak respectively, which should not be the case. I am not able to understand why this is happening. I think that it is due to some delays in the MOS, but that reasoning is not sufficient. Any help is appreciated.

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  • \$\begingroup\$ Plot out all the internal nodes, with 0.02 nanosecond time steps. \$\endgroup\$ – analogsystemsrf May 1 '19 at 5:31
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The pulses you are seeing as "peaks when both inputs transition" is totally due to different time delays through the circuit the from either input to the output.

Logic chip manufacturers go to great lengths to design circuits in an attempt to equalize the logic delays through the circuit so as to minimize the effect that you are seeing. Invariably this leads to a circuit with more transistors and careful tuning of the various device sizes (channel widths and lengths) to get the logic paths more in line with each other.

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  • \$\begingroup\$ Yes, the IC designer should equalize the delays as much as possible. But, since no matter what they do, there will still be a possibility of glitches during simultaneous input transitions, the user of this IC should be aware of this possibility and must never allow these glitches to cause the system to fail. This is why synchronous designs are often preferred. \$\endgroup\$ – Mattman944 May 1 '19 at 6:12

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