# Can CMRR of a data acquisition input be measured this way?

I want to check a data acquisition input or overall CMRR of a signal chain roughly by a simple method.

Normally for a daq input CMRR is defined as:

CMRR = 20×log10(Vin/Vout)

where Vin is the common mode voltage Vcm applied at both inputs.

But in practice I hesitate to use the above formula. It is because when I short the inputs together the Vout is not zero. It has some offset with standard deviation.

So first I short the inputs I obtain x at the output. x represents output voltage and xrms is the rms value of x.

Then I apply purse sinusoid common mode voltage by a function generator. I call the rms value of common mode input as Vrms and the output as a.

Finally I double the pure sinusoid input common mode voltage as 2Vrms and I call the output as b.

I tried to illustrate these by the following drawing:

Is the following approach to estimate the CMRR mathematically correct?:

CMRR = 20xlog10(ΔVcm_rms/ΔVout_rms)

ΔVcm = 2Vrms - Vrms = Vrms

ΔVout_rms = (a_rms - x_rms) - (b_rms - x_rms)

CMRR = 20xlog10[V_rms / (a_rms - b_rms)]

Is the above a valid estimation to verify the claimed CMRR?

• Just a note on the first configuration, " when I short the inputs together the Vout is not zero". It's most likely due to Vos, the input voltage offset of that particular opamp. May 1, 2019 at 15:15
• Its not an opamp maybe an inAmp since it is about a data acquistion board input. Drawing is just to illustrate the connections. May 1, 2019 at 15:18
• Instrumentation amp is just a special configuration of opamp(s), sometimes made discreetly sometimes integrated into a single chip. Either way, they all still have a Vos, check the datasheet. May 1, 2019 at 15:23
• It is a board input mccdaq.com/PDFs/specs/USB-1608G-Series-data.pdf May 1, 2019 at 15:48

CMRR not just the Common Mode gain, Acm but the rejection ratio of CM gain to DM gain.

Input $$\V_{{IN}_{cm}}=\dfrac{V_{in-} + V_{in+}}{2} \$$

$$\A_{cm}=\dfrac{V_{{OUT}_{cm}}}{V_{{IN}_{cm}}} \$$ , cm = common mode
$$\A_{dm}=\dfrac{V_{{OUT}_{dm}}}{V_{{IN}_{dm}}} \$$ , dm = diff. mode

$$\CMRR=\dfrac{A_{cm}}{A_{dm}} \$$

By nulling input offset to get 0V out, then you can apply Acm input and divide by open loop gain.

simulate this circuit – Schematic created using CircuitLab

The grounded clock + sine must be within the CM input range. Then if you have a DAC compare output SINE with input SINE and adjust ratios of Vdm/Vcm until you can see results. Or you can sweep Vdm instead of a pulse just as long as it is not harmonically related to SINE Vdm .

There may be better ways of analyzing CMRR results with a Spectrum Analyzer or a WAV file on Audacity.exe

• It is a board I cannot do nulling mccdaq.com/PDFs/specs/USB-1608G-Series-data.pdf May 1, 2019 at 15:47
• I can just apply inputs and obtain outputs yet Im looking for an okay method May 1, 2019 at 15:49
• You can on the 8x2 mode fIN = 60 Hz, all input ranges: 86 dB. But I suggest if you have a CM problem , look elsewhere. Balance error on {source Z, cable impedance vs f, load, loop area, CM noise level etc} May 1, 2019 at 15:53
• i dont have a problem I just want to measure myself CMRR of the board. May 1, 2019 at 15:57
• OK If you have a DAC on-board generate a triangle test pattern to calibrate it then use it to show results. May 1, 2019 at 16:03

A better way to measure CMRR is with a circuit like this:

The common-mode rejection ratio (CMRR) of an op amp is the ratio of apparent change of offset resulting from a change of common-mode voltage to the applied change of common-mode voltage. It is often of the order of 80 dB to 120 dB at dc, but lower at higher frequencies.

The test circuit is ideally suited to measuring CMRR (Figure 6). The common-mode voltage is not applied to the DUT input terminals, where low-level effects would be likely to disrupt the measurement, but the power-supply voltages are altered (in the same—i.e., common—direction, relative to the input), while the remainder of the circuit is left undisturbed.

In the circuit of Figure 6, the offset is measured at TP1 with supplies of ±V (in the example, +2.5 V and –2.5 V) and again with both supplies moved up by +1 V to +3.5 V and –1.5 V). The change of offset corresponds to a change of common mode of 1 V, so the dc CMRR is the ratio of the offset change and 1 V.
Source: https://www.analog.com/en/analog-dialogue/articles/simple-op-amp-measurements.html

## EDIT

Now that you mention an ADC, it's a bit different.

$$CMRR = \frac{A_{Diff}}{A_{CM}}$$

where

$$A_{Diff}= \frac{\Delta Output Code}{\Delta Differential Voltage}$$ $$A_{CM}= \frac{\Delta Output Code}{\Delta Common Mode Voltage}$$

Source: m.eet.com/media/1175625/c1022edited.pdf

So one way this could be tested is by fixing the differential voltage on one side of the ADC with a voltage source (like an isolated power supply with low noise for V1 if you have a really nice one at hand, a battery with a voltage divider might work also) and then vary the common mode voltage. Ideally the output code shouldn't change.

simulate this circuit – Schematic created using CircuitLab

• Comments are not for extended discussion; this conversation has been moved to chat. Any conclusions reached should be edited back into the question and/or any answer(s). May 1, 2019 at 21:41