# Reducing the range of a D flip-flop frequency detector

I'm designing a frequency tracking circuit and I came up with a circuit that tracks frequencies from Fclk to Fclk/2:  However, it would be very nice if the bandwidth was a bit narrower, from Fclk to Fclk/1.5, for a higher sensitivity (see red line above), is there a way to modify this circuit to achieve that? Or maybe there are other circuits with similar behavior?

• What a fantastic Question +1 .What a useful circuit .I am too scared to answer it . May 2, 2019 at 10:36
• Does this circuit not depend on the beat-note of the sampling behavior between the two (un-phase-locked) input frequencies? May 2, 2019 at 12:20
• @analogsystemsrf no, it doesn't. This circuit runs on a MAX II CPLD right now, no problems whatsoever. I presume, the CLK fed to both DFFs provides some kind of a phase-lock but I'm not sure, I got this circuit accidentally while experimenting with PFDs. May 2, 2019 at 12:36
• Or maybe the beat notes are well beyond the output filter cutoff frequency (15 kHz)? May 2, 2019 at 12:42

The circuit is a simple edge detector. The output has a variable pulse density that's based on the ratio between the input frequency and the reference frequency.

For frequencies up to Fclk/2, every input edge (rising or falling) produces an output pulse. Above this frequency, some edges are missed, reducing the number of output pulses.

I assume that the triangle plot represents the average value of the output signal for various input frequencies. Obviously, this graph has a periodicity that's related to Fclk, and the slope of the graph varies as well.

If you want a steeper slope over a particular range, you just need to reduce Fclk until the graph has the slope you need over the required range. You'll be undersampling the input clock, but that's OK in this kind of application.

Or maybe there are other circuits with similar behavior?

If your circuit produces an average output voltage that represents how close the two frequencies are to each other then, just use an analogue comparator on the filtered output where the threshold of the comparator is set to some level slightly below Vcc (say at 75% of Vcc). This can be easily set by a potentiometer.

• I need to keep a linear relationship at the output, not just a digital output whether the frequency larger or lower than reference. By the way, this is the part of an FM receiver that has to lock the LO to the input carrier, I remember you designed something like that, how did you implement the tracking circuit? In my case the carrier can vary between 49-35 MHz and this circuit does the job almost perfectly. May 2, 2019 at 12:05
• You will still have a linear relationship; the comparator is there to tell you that you have gone beyond the range that you wish to capture. If it's data then I made sure the data was scrambled and used an integrator on the demodulated data to nudge the LO back in line. Is this what you mean? May 2, 2019 at 13:29