I've written a component where I use the same variable for the input and output parameter of a procedure. A reduced example looks like this:
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity var_test is port ( iClk : in std_logic; iReset_n : in std_logic ); end entity; architecture behaviour of var_test is procedure incr( iVar : in signed(15 downto 0); oVar : out signed(15 downto 0) ) is begin oVar := iVar+1; end; begin process variable vVar : signed(15 downto 0) := (others => '0'); begin wait until rising_edge(iClk); if iReset_n = '0' then else incr(vVar, vVar); end if; end process; end behaviour;
vVar in the simulator I expect it to be a counter. This is indeed the behavior I'm seeing when setting the VHDL standard to 2002 in ModelSim 10.5b. However, when selecting VHDL 2008 the variable value is undefined (displayed as 'X') after the first rising edge after reset. Was there a change regarding this behavior between these VHDL standards? Or is this code illegal and just worked by accident?