# VHDL Procedure - Same variable for input/output parameter

I've written a component where I use the same variable for the input and output parameter of a procedure. A reduced example looks like this:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity var_test is
port
(
iClk        : in  std_logic;
iReset_n    : in  std_logic
);
end entity;

architecture behaviour of var_test is
procedure incr(
iVar : in  signed(15 downto 0);
oVar : out signed(15 downto 0)
) is
begin
oVar := iVar+1;
end;
begin

process
variable vVar : signed(15 downto 0) := (others => '0');
begin
wait until rising_edge(iClk);
if iReset_n = '0' then
else
incr(vVar, vVar);
end if;
end process;

end behaviour;


When observing vVar in the simulator I expect it to be a counter. This is indeed the behavior I'm seeing when setting the VHDL standard to 2002 in ModelSim 10.5b. However, when selecting VHDL 2008 the variable value is undefined (displayed as 'X') after the first rising edge after reset. Was there a change regarding this behavior between these VHDL standards? Or is this code illegal and just worked by accident?

• Hm.....interesting......I just checked in 10.4a....same problem May 2, 2019 at 12:40
• If you just need a solution that works, you could write either an inout port or a pure function returning oVar, but no idea why this doesn't work, so no answer to the question. May 3, 2019 at 8:26
• Do you have a support contract? This sounds like a very peculiar thing that should be checked with a ticket to the makers of the very expensive software. Kinda hard for community debugging, also, given the exclusivity of it. Nov 30, 2019 at 0:16

## 1 Answer

I have changed your function to give a value on reset as follows:

wait until rising_edge(iClk);
if iReset_n = '0' then
vVar := (others => '0');
else
incr(vVar, vVar);
end if;


I don't know how it works without this initialization for previous VHDL versions (it shouldn't), but it works with it under VHDL 2008