Decoupling cap routing on a 4 layer PCB

I would like to place some decoupling caps for an IC. The IC is on the top while the caps will be on the bottom, opposite side. How should I route them:

• A single VIA that connects the IC pin, power plane and cap

• Two VIAs, one that connect cap with power plane and another that connects cap with IC pin

Edit: More detailed picture of the 2 scenarios

(But first, I want to thank everyone for the great answers and comments!)

I have decoupling cap. One pin of the cap is connected to the ground plane by a VIA. That is for both scenarios. The other pin of the cap will be connect a) to power, b) to IC input. Thus, three things have to be connected together ultimately: IC pin, power, cap pin.

• Scenario 1: A VIA connects the 3 of them, that is a trace from IC pin goes to the VIA, the VIA is goes through power plane and actually connects with power plane, a trace connects this very same VIA with the cap pin.

• Scenario 2: A VIA is connected to power plane and a trace connects cap pin with this VIA. Then another VIA connects the IC pin with the that trace, but the second VIA although it goes through the power plane does not connects with it. So you have two VIAs: one that connects the cap with the power plane and another that connects the cap with the IC pin.

• The main thing is to limit the area enclosed by the current path. That is the path from the IC power pin through the tracks, vias and planes back to the IC ground pin. The area in 3D of this path is what matters. May 2, 2019 at 14:26
• I would not isolate the vias from the planes. Using the plane will usually help minimize the loop path. May 2, 2019 at 19:51

It actually does not matter too much, according to Henry Ott's book on EMC. Proximity, trace length, and loop size matter more.

If the IC and cap are on different sides of the PCB, placing both vias along the edge of the capacitor pad side (rather than the ends) so they are closer also reduces inductance since magnetic fields of opposite currents in the via cancels out. Multiple vias also helps. Note this also applies to connecting IC power pins to the power and ground planes. Those are part of the loop too.

From Electromagnetic Compatibility, Henry Ott 2009

Similarly, placing two caps on the same side on opposite sides of the IC does something similar since the loop currents flow inside each loop in opposite directions and the magnetic overlap a fair amount if the loops are close to each other. From Electromagnetic Compatibility, Henry Ott 2009

So you can see that the first requires a pair vias for both the cap and pins, but the vias can be tightly coupled, while the second requires longer traces/loops but no vias. It's twelve of one or a dozen of the other.

• If I understood correctly what you wrote, then I can simply connect with a single VIA the pin-power plane-cap since what matters is the loop area. What feels wrong for me, though, is that since the power plane is the middle of both components, then the cap will have no effect to the actual pin which is supposed to decouple. It is unintuitive to me. May 2, 2019 at 15:03
• It's a current loop, so everything is already in the middle of everything else. Think of the high frequency current loops as being INDEPENDENT of the power supply. The cap's own charge is the supply in this (AC analysis). The planes and power supply are not the source of high frequency energy. The plane is just a path for it to flow between the IC and actual source (the cap), not a power source for high frequency currents. May 2, 2019 at 15:12
• @Manos the fact the supply feed line/plane arrives in the middle of the path between the cap and the chip supply pin, or before the cap, or even on the other side of the chip pin relative to the cap, isn't much relevant. The only thing that matters is that there exists a very low inductance path between the supply pin and the local supply (provided by the decoupling cap). If you fulfill this, who cares where the actual supply is fed from?
– dim
May 2, 2019 at 15:16
• @dim Thank you both for your detailed explanations, think I understood (finally!). May 2, 2019 at 15:19

Minimize the total area, and the enclosed volume, of the current-loop.

Thus placing caps on the back, UNDER the IC's VDD/GROUND pin-pairs, is a good mindset.

Think in 3_D, draw sketches in 3_D, and minimize the total area and total volume.

Important is that VCC first connects to the Cap, then from there you go to the IC pin. If you need a second via to get VCC to the bottom layer at this place, then that's the way to go.

The bypassing effect exists, because every trace on the PCB has a certain inductance. If there is a change in current draw, the inductance allows the current flow to change only slowly. The longer the trace, the stronger is this effect (I guess you knew that already). Now it is pretty easy to imagine, that the capacitor can act way faster, when the supply current is typically already flowing along its pin. If now the supply voltage collapses (or has some ripple) the current delivered by the capacitor is producing a dI/dt only at the leads of the cap. The rest of the trace does not see a change in current (in an ideal scenario).

Nevertheless the bypassing would be significantly better, if the cap was also on the PCB side of the IC, so that you need no via at all (at least not between cap and IC), because a change in current draw (e.g. due to some clock of the chip) IS still producing a dI/dt on the trace to the capacitor.

• "significantly better, if the cap was also on the PCB side of the IC" If you're lucky enough that the power pins are right next to each other and are spaces the same length of the cap and you have enough space to practically land it on top of the pins. That's rare though but it's the dream. May 2, 2019 at 14:38
• Important is that VCC first connects to the Cap, then from there you go to the IC pin. I thought this too for the longest time (this is what I learned), but after further reading, research, and experimentation it really doesn't make a difference whether Vcc "hits" the IC pin first or the cap first. The physical proximity of the capacitor to the pin is what is important. May 2, 2019 at 16:21