If I can get away with, I will use 6-layer design where I get two dedicated GND planes, L2 and L5, which creates strong reference plane for traces on L1, L3 and L6.
When you're working with 4 layers, you have no such luxury. If your board all runs from specific voltage, e.g. 3.3V, you're pretty much good to go, the n+1 bypass caps on all the devices tightly couple the VCC plane to GND. However, as often happens, you've got 5V, 3.3V, 2.5V, 1.8V and what not. That obviously creates a mess of copper flood edges on the power plane. Sometimes you may be able to stitch the power planes together at point of traverse or route traces entirely around the plane gap but this is not always viable.. Ideally you'd also like a stitching cap where you change AC traces between GND referenced and power referenced planes.
Would using surface layers for power be a reasonable alternative to using dozens of stitching caps? The only downsides I see is some extra work creating the origami of copper flood carrying the power and perhaps some EMI issues if you're using e.g. cellular module.
Update The stack-up is L1=>L2 0.1mm, L2=>L3 1.27mm, L3=>L4 0.1mm, which gives you 50R trace impedance with reasonable line widths. Plane assigments are
- Component / Signal /GND
- VCC (3 separate voltages in this design)
- Signal / GND
I have avoided traversing plane edges as a matter of course, but this still leaves the issue of signal X not being driven by voltage Y.