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If I can get away with, I will use 6-layer design where I get two dedicated GND planes, L2 and L5, which creates strong reference plane for traces on L1, L3 and L6.

When you're working with 4 layers, you have no such luxury. If your board all runs from specific voltage, e.g. 3.3V, you're pretty much good to go, the n+1 bypass caps on all the devices tightly couple the VCC plane to GND. However, as often happens, you've got 5V, 3.3V, 2.5V, 1.8V and what not. That obviously creates a mess of copper flood edges on the power plane. Sometimes you may be able to stitch the power planes together at point of traverse or route traces entirely around the plane gap but this is not always viable.. Ideally you'd also like a stitching cap where you change AC traces between GND referenced and power referenced planes.

Would using surface layers for power be a reasonable alternative to using dozens of stitching caps? The only downsides I see is some extra work creating the origami of copper flood carrying the power and perhaps some EMI issues if you're using e.g. cellular module.

Update The stack-up is L1=>L2 0.1mm, L2=>L3 1.27mm, L3=>L4 0.1mm, which gives you 50R trace impedance with reasonable line widths. Plane assigments are

  1. Component / Signal /GND
  2. GND
  3. VCC (3 separate voltages in this design)
  4. Signal / GND

I have avoided traversing plane edges as a matter of course, but this still leaves the issue of signal X not being driven by voltage Y.

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I would say it is not reasonable if you want two outer signal/component layers because what are you going to do with the two inner layers? Make them both ground planes? It's a much bigger waste than just using stitching caps. You might as well go with a 2 layer board and deal with a similar level of routing difficulties but with greatly reduced cost

You can try to locate your vias near pre-existing decoupling caps if possible.

However, if you are going to place all components on one layer, you could just go signal/component-gnd-signal-pwr. The ground plane is now the reference layer for both signal layers due to adjacency. No more stitching caps to worry about and you still have two signal layers so you can criss cross with no origami required. Plus that inner signal layer is shielded. What more could you want?

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  • \$\begingroup\$ All of the components are on top layer so that's not a problem. However half of the traces are on bottom layer due to preferred routing direction. It's those tracks switching from top layer with strong ground plane reference to bottom layer with weakly coupled VCC plane that's my concern. And yes, the layers are assigned GND-GND-VCC-GND with tracks on top and bottom layer. Maybe it'd be enough just to stick stitching vias near traces switching layers to allow coupling to shift from L2 to L4 surface copper. \$\endgroup\$
    – Barleyman
    May 3 '19 at 13:58
  • \$\begingroup\$ @Barleyman I was editing my post. Might answer your question directly now. \$\endgroup\$
    – DKNguyen
    May 3 '19 at 13:58
  • \$\begingroup\$ The snag with that suggestion is that L1=>L2 and L3=>L4 are 0.1mm prepregs while the core is 1.2 to 1.4mm. So you're not going to get a nice coupling across that core.. That's the same reason a 2-layer board wouldn't work, unless you're willing to put up with waveguides that's a lot more work and require shielding vias. In any case, I just went with the traditional route i.e. added 8 stitching vias to provide VCC-GND coupling for "fast" signals and added a bunch of stitching vias where traces change layer to provide GND plane -> surface copper coupling. \$\endgroup\$
    – Barleyman
    May 3 '19 at 14:47
  • \$\begingroup\$ @Barleyman 0.1mm? Is this an embedded capacitance board? You need 0.05mm spacings to get 500pF/in^2 and the target is 1000pF/in^2 to be effective above 50MHz., so you need two pairs of coupled power-ground planes to reach that even on an embmedded capacitance PCB. I think you are splitting hairs with plane coupling when the spacing is too large for it to even matter. \$\endgroup\$
    – DKNguyen
    May 3 '19 at 14:53
  • \$\begingroup\$ Not at all. 0.1mm prepreg + 150µm trace = 52R, fairly compact. You also don't have to provide excessive separation between traces, 0.3mm works just fine. This kind of build is actually pretty common even with prototype oriented fabs. They may have 0.12 or 0.15mm prepreg instead but it doesn't change the equation that much. \$\endgroup\$
    – Barleyman
    May 3 '19 at 15:00

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