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I'd like to get complementary output from a 555 timer. I've seen previous suggestions of using a D Flip Flop, which is a fine suggestion, however that halves the frequency at the outputs of the flip flop, so I'd have to double the 555 output frequency. Is there a better approach where I don't have to double the 555 frequency to get a complementary output?

I imagine doubling 555 frequency for semi-high frequency applications would increase power consumption and possibly be less stable, or less precise, if I approach the max frequency limit of the 555. Which, in my project, I would be getting close to the upper limit stated on the data sheet and that's why I'm interested in a solution that doesn't double the 555 frequency. i.e., I'd possibly have to look to a clock generator solution more complicated than a 555, capable of higher frequencies, which I'd like to avoid if I can.

If it matters, or if you're curious, I'm aiming for a 1.4 MHz complementary clock signal with a LMC555 (or something similar). Doubling that for the flip flop, makes the 555 output 2.8 MHz. fmax in the data sheet is 3 MHz, so very close to max.

Also, I do need some degree of adjustability of the output frequency. i.e., in the case of a 555, a trimmer capacitor to adjust the frequency.

EDIT: In the comments I mentioned I'm looking for fairly precise complements of the clock output signals, without much error between the two, and someone asked me to clarify this. So I'll say these complementary clock signals are to drive a differential RF (analog) mixer. I think any error between the complementary clock signals will distort the mixer output, however if I'm wrong on that, feel free to correct me.

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  • \$\begingroup\$ Can you just add a complimentary output by adding a MOSFET and a resistor? \$\endgroup\$ – evildemonic May 3 at 19:28
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    \$\begingroup\$ You can use any kind of inverter: logic gate, transistor or FET, or even a second 555. But there might be consequences for the exactness of the inversion (different high times, overlaps, different edges, etc.) \$\endgroup\$ – Wouter van Ooijen May 3 at 19:33
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    \$\begingroup\$ You should have been more clear in your original question. Please edit the question and explain exactly and quantitatively what you mean by "fairly precise complements". \$\endgroup\$ – Elliot Alderson May 3 at 19:33
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    \$\begingroup\$ "I think any error between ..." if this statement is true as typed, then we are all doomed. We're engineers. We recognize that there are always errors. The question "are there errors" is exactly equivalent to "look me in the eye and say 'yes'". So the question that you need to ask is "how much error can I stand". If you've already chosen a mixer, I suggest that you post that as a question -- give a part number, show a proposed schematic, and ask "what happens if the input to my mixer isn't perfectly complimentary?" \$\endgroup\$ – TimWescott May 3 at 19:54
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    \$\begingroup\$ @acker9 Since you need \$1.4\:\text{MHz}\$ and the LMC555 is capable of \$3\:\text{MHz}\$ (unusually good), you really are best adding a divide-by-2 DFF with \$Q\$ and \$\overline{Q}\$ outputs. You can buy pretty good performance, then, by selecting an appropriate DFF. I agree with Spehro about this. Don't mess around. \$\endgroup\$ – jonk May 4 at 3:25
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You can use the VCO portion of a 74HC4046 plus an inverter. If you want even more aligned edges, clock a dual D FF with the true and inverted signals as inputs.

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  • \$\begingroup\$ Can you explain how feeding the output of the clock generator to a dual D flip flop gets "even more aligned edges?" I'm not clear on how the outputs of the dual flip flops improve upon the inputs. \$\endgroup\$ – acker9 May 3 at 20:27
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    \$\begingroup\$ You clock it on the opposite edge after the Q and /Q inputs are stable. With an inverter the output cannot change until some time after the input transition, not many ns but >0. With a FF the outputs the outputs will change closer to simultaneously. \$\endgroup\$ – Spehro Pefhany May 3 at 20:31
  • \$\begingroup\$ I'm accepting this one as the best answer because #1) @jonk's comment convinced me there's probably nothing better than a div-by-two DFF. #2) Nearly everyone said the 555 is a bad choice. #3) Other answers that involve an inverter are interesting but perhaps add more complexity over the divide-by-two approach, especially if delay circuits are needed. It would be difficult to keep the delay network tuned with variable frequencies. This answer mentions an inverter too, but by combining this answer with jonk's comment, conclusion of: something like the 74HC4046 coupled with a divide-by-two DFF. \$\endgroup\$ – acker9 May 4 at 15:31
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You can add a MOSFET and a resistor to add a complimentary output like this:

schematic

simulate this circuit – Schematic created using CircuitLab

You can buffer the two outputs if they need matching properties.

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    \$\begingroup\$ You might also want to add a version with the the PMOS version on the non-inverted output if the OP wants complimentary outputs with the same output impedance. \$\endgroup\$ – DKNguyen May 3 at 19:36
  • \$\begingroup\$ Toor: Do I have to match NMOS and PMOS transistor properties (length, width, etc) to achieve the same output impedance that you mention? \$\endgroup\$ – acker9 May 3 at 19:42
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    \$\begingroup\$ @acker9 The resistor used would probably dominate. But if you search complimentary PMOS/NMOS transistors that are located in the same package, quite a few of them are designed to match as closely as possible. The RDson won't match but that won't be of any importance since the resistor will dominate. The gate charges and capacitances is the target of the matching. \$\endgroup\$ – DKNguyen May 3 at 19:45
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    \$\begingroup\$ The resistors you use are controlling the output impedance. To match the transistors you look at gate capacitance and total charge. Many MOSFETs will list a complimentary partner in their datasheet if there is one. \$\endgroup\$ – evildemonic May 3 at 19:53
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    \$\begingroup\$ I'm not sure why you'd go to all that trouble when you can get six CMOS inverters in a single package. \$\endgroup\$ – Dave Tweed May 3 at 19:58
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Complementary clock output from a clock generator such as a 555 timer using simple digital logic.

The 555 timer is an absolutely terrible clock generator (probably over 2% error/drift).
If it's good enough, at 1.4MhZ then you have a clock period of about 700ns.

The rise and fall times of the 555 are terrible too at about 100ns.

However assuming again that it meets your needs and you want close complimentary edges, you need to provide buffering and level detection.

The best way would be to use something like a 74HC14 Schmidt trigger inverter. To get the edges aligned you first need to provide the level sensitive trigger and then provide a way to adjust the edges so that they align to your requirements (you don't specify this at all so I have no idea what constitutes "precise complements").

schematic

simulate this circuit – Schematic created using CircuitLab

The 74HC14 has a 'typical' delay of 11ns, but it could be up to about 25ns worst case as shown below.

enter image description here

You can also buy Clock delay lines such as the Maxim DS100L, but I doubt you need this level of accuracy.

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