partial schematic showing quartz crystal and capacitors

I read that it is recommended to connect 2 grounded capacitors to both ends of the quartz crystal. But that doesn't make any sense to me.
Since capacitors have no resistance, wouldn't that make it so the electricity from the MCU flows directly into ground?
And if it doesn't, what's the point anyway? They aren't connected to a signal receiver, so they can't act as decouplers to stabilize the signal anyway.
They just seem to suck away the signal.
So what's the point of them and why are there 2 of them?

  • 1
    \$\begingroup\$ Why didn't you try to Google first, "why do you need load capacitors for a crystal"? \$\endgroup\$ May 4 '19 at 18:01
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    \$\begingroup\$ cuz I didn't find a answer that made sense to me \$\endgroup\$ May 4 '19 at 18:02
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    \$\begingroup\$ Suggest you google Pierce Oscillator and come back if there is something that is not clear. You can think of the two capacitors as in series across the crystal. \$\endgroup\$ May 4 '19 at 18:02
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    \$\begingroup\$ @user2741831 Probably better to read this appnote. Partly, a manufacturer of an MCU makes their class-A inverter run "hot" because they can't trust their buyers' knowledge and after-sale support calls are expensive. Partly because of so much over-drive, it's possible that the crystal might fall into an odd harmonic. Also, crystals aren't all the same quality and while some won't fall into odd harmonics so easily, others will. Regardless, the external caps dampen odd harmonics & provide what's needed for parallel mode. All are happy. \$\endgroup\$
    – jonk
    May 4 '19 at 18:06
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    \$\begingroup\$ @user2741831 I'm afraid that your understanding of how capacitors work is fatally flawed. Until you fix that, you're not going to have a basis for understanding a crystal oscillator. \$\endgroup\$
    – TimWescott
    May 4 '19 at 18:27

Ok, I got the question. The answer is:

Crystals must be connected in a feedback loop of some amplifier, in some way or another. As such, the crystal will be subjected to parasitic circuit and board capacitances, aka "loaded". One can't avoid this "load".

At the same time the frequency of this "feedback" filter [electro-mechanical resonance] depends on the load capacitance, to a certain degree (called "crystal pullability", about 8ppm per 1pF of load). Therefore, to get a well-defined frequency of oscillations, all crystals are tuned at certain specific load, 12pF, 20pf, etc. during manufacturing stage, which becomes a part of crystal specification. The task of a designer is to meet these specifications if they want a good specified frequency.

There are two caps because the load is effectively split between output capacitance and input capacitance in the typical Pierce Oscillator schema. So the caps are essentially connected in-series. Thus, a crystal specified for 20 pF load should use two 40 pF caps.

Now, a good circuit designer understands that the IC pins have certain inherent capacitance (2-4 pF), and PCB traces and pads also have some capacitance (3-5pF, depending on particular layout). So these parasitic capacitances be better accounted in the circuit, so the actual caps are usually smaller than the 40pF as per example above, and could be 22-27pF after all corrections. In some cases no caps are required if the pin/trace/pad capacitance already meets the crystal specs.

  • \$\begingroup\$ I assume this is correct but I don't think I understand it. I'll check it off once I do \$\endgroup\$ May 4 '19 at 18:33

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