In my VHDL testbench, I have a configurable parameter DATA_WIDTH which is set to power of 2 such as 16-bits.
I want to generate random signed numbers (2's compliment) of bit width as DATA_WIDTH. For example if DATA_WIDTH is 16 bits, then I want to generate random numbers in range -32,768 to 32,768 (all range inclusive).
As of now I am doing following (snippet of VHDL code, not complete):
variable W : natural := 16; variable seed1, seed2 : positive := 1; variable x_real: real := 0.0; variable x_int : integer := 0; variable data_vec std_logic_vector(W-1 downto 0) := ( others =>'0' ); uniform( seed1, seed2, x_real ); x_int := integer(floor(x_real * real(2**W))); data_vec := std_logic_vector( to_signed( x_int, data_vec'LENGTH ) )
However, when I run the testbench simulation, I get following warnings from Modelsim:
Warning: NUMERIC_STD.TO_SIGNED: vector truncated
There is a related question, however the answer in that post doesn't offer solution using standard VHDL libraries but using Open Source VHDL Verification Methodology.