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I am finalizing my design which connects a USB Controller (FT601) with the FPGA (MachXO2). There is last thing I am not particularly happy about and I would like your feedback on that.

In the following image, the two vias connect 2 supply sources (3.3V and 1.0V respectively) to the IC while the surrounding traces are LVCMOS33 data lines.

Power and data traces

The PCB is 4 layer stackup, second plane is ground plane. The data traces are 8 mil wide with an impedance of approximately 54Ω. The lines are bidirectional, and both ICs output at 50Ω impedance, so they are matches. Rise/Fall time is 0.8 to 1.2 ns.

The power lines are 7 mil wide. I made them 1 mil shorter to gain a little bit more space between them and the data lines. They are properly decoupled, since I have put the necessary caps exactly on the opposite side. Their length is around 200 mil.

Question: Is there a strong possibility that the power supply will affect the data lines or vice versa, resulting in an instability of the IC?

Simulation in Altium with a proper IBIS file reveals a small fluctuation of 30-40 mV of the power lines affected by the data lines.

In case you are wondering I did not place the supply internally of the footprint because is a QFN with a large pad connected to ground so I cannot risk a short-circuit. Thanks in advance.

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  • \$\begingroup\$ It depends on impedance of decoupling cap at 300 MHz and ratio to supply/return impedance lines times current during rise /fall time \$\endgroup\$ Commented May 5, 2019 at 20:24
  • \$\begingroup\$ Where are your ground connections? \$\endgroup\$
    – The Photon
    Commented May 5, 2019 at 20:34
  • \$\begingroup\$ @ThePhoton Ground connections are to the left behind the pads. I reuse the vias of the heatsink pad which are connected to the ground. It was the topic of my last question. \$\endgroup\$
    – Manos
    Commented May 5, 2019 at 20:37
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    \$\begingroup\$ It doesn't matter how much a trace can deliver, and whether or not there are other pins. What matters is how inductive the trace is, and how much instant current it can deliver to local I/O bank. And you have no bypass cap in close proximity. You have 32+ bit parallel bus, and consider if all lines are switched at once, in under 1 ns, with drive of 8 mA, it is already 256 mA. You better check the MachX guides on how many parallel bits your part can handle, and look at their layout suggestions for power distribution. By not placing the power in inner space you are risking much more than shorts. \$\endgroup\$ Commented May 5, 2019 at 22:17
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    \$\begingroup\$ Consider this: your IC delivers dV=3V in 1ns (10e-9). If the pin has 10pF load (5pF for pin/pad and 5pF for trace), I = C dV/dt = 3e-2, or a spike of 30 mA per pin. This can be about 1 A in 1-ns-short spike for the 32-bit bus, so your local power on I/O bank will sag, and drug down other control lines disrupting the entire data protocol. Think about this, and better put a good array of low-ESR caps around solid power rails, not 7 mils wide. \$\endgroup\$ Commented May 5, 2019 at 22:36

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