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This a more elaborate phrasing of my previous question on the subject, which did not get much love. I would appreciate a clear and thorough answer since it is my last question (after a long journey) before I finally send the PCB for manufacturing (cross fingers).

I have 4-layer PCB (signal, ground plane, power plane, signal). On the top side, there is a QFN-76 IC which has a heatsink pad on the bottom. According to the datasheet, it is connected to the ground and should be connected to the ground plane by vias, which I have done so as you may see:

PCB Top

As said, those vias, and consequently the pad, are connected to the ground plane. On the other side of the PCB, I have placed the required decoupling caps physically as closer as I could near the corresponding power pins and I have used the vias of the heatsink pad in order to connect them with the ground plane, as depicted below:

PCB Bottom

My Questions

  • Is this a bad practice? Is it possible to cause any problems? If so, what is the proper way to do?
  • On the first image, top of the PCB, I have also connected some of the IC ground traces to the pad. Is this, also, a bad practice?
  • One thought of mine was to create an identical pad on the bottom of the PCB, using the same vias to ground as well, for the caps to connect. What do you think of that?

As always, all your recommendations and guidelines are more than welcome. Thanks in advance.

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    \$\begingroup\$ If you wanted elaboration, you could have just edited your other post and that bumps it back to the top. This could count as double-posting. \$\endgroup\$ – DKNguyen May 7 at 15:42
  • \$\begingroup\$ @Toor I thought of that but I rephrased it completely now that I have a more thorough grasp on it, so it is essentially a completely different. Also, I started a new question because I was planning to add bounty, but after posting I figured out I cannot yet. \$\endgroup\$ – Manos May 7 at 15:44
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Is this a bad practice? Is it possible to cause any problems? If so, what is the proper way to do?

Not necessarily, but be aware of two things:

  • The inductive pathway to ground is increased with traces slightly, this does have an effect with high frequency and increasing the ESL of the caps slightly. If you want to find out what the effect is, find the ESL of the cap then find the inductance of the trace with a PCB trace inductance calculator. Generally it's a good idea to place the bypass capacitors vias to ground close to the capacitors.

  • The thermal pathway for the QFN is increased. The more traces you sink to the QFN's heatsink, the more heat it dissipates and the harder it is to solder the QFN part on and off. This is also minimal, but something to be aware of.

On the first image, top of the PCB, I have also connected some of the IC ground traces to the pad. Is this, also, a bad practice?

No, I think it's a good practice as all the grounds of the QFN part have a common mode and are at the same potential, which I think is good (maybe there are reasons this is bad).

One thought of mine was to create an identical pad on the bottom of the PCB, using the same vias to ground as well, for the caps to connect. What do you think of that?

This would also be ok, because paralleling vias also decreases inductance, you can think of each via as an small inductor at high frequencies. Parlalling inductors decreases overall inductance.

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  • \$\begingroup\$ Thanks for your answer. I was thinking of creating an identical pad on the bottom side for the reason you mentioned - to decrease the inductance of the pathway to the ground plane. Additionally, it will decrease the length of the traces that connect them to the vias. Do you think that this will increase the difficulty of soldering to a significant degree? If not so, then I will proceed with this implementation. Again, thanks for answering. \$\endgroup\$ – Manos May 7 at 18:48
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    \$\begingroup\$ It really depends on the part, If I'm prototyping these by hand I usually tend to avoid large thermal junctions because it makes it harder to solder. I don't usually worry about it if I send the design to an assembly house. \$\endgroup\$ – Voltage Spike May 7 at 18:51
  • \$\begingroup\$ meta.stackexchange.com/questions/126180/… \$\endgroup\$ – Voltage Spike May 7 at 18:51
  • \$\begingroup\$ If it is going to benefit the design integrity-wise then an extra work of on the hand soldering part is acceptable, I only worry if it makes it too difficult near to impossible for hand soldering. I have no prior experience with QFN and heat dissipation. Regarding the thanks, I understand, I am just kind and respect your time for answering. ;) \$\endgroup\$ – Manos May 7 at 18:56

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