I've designed a circuit board with a Microchip switch (KSZ9897) going to a Ethernet-to-VDSL module (LX200V20).

The PHY ports between the two devices are connected using a transformerless connection as shown on Figure 4 in this application note (http://ww1.microchip.com/downloads/en/AppNotes/ANLAN120-UNG.pdf).

By default with auto-negotiation & auto MDI-X enabled, the switch establishes a 10 Mbps, full-duplex link. I am expecting a 100 Mbps link since both devices are 100-BaseTX compatible and I've confirmed that by decoding the LCW (link-code-word) from their fast link pulses.

I have also tried a forced speed connection (disabling auto-negotiation). For 100 Mbps & Full-duplex, I can see some idle traffic on both RX and TX pairs, but the link does not come up. For 10 Mbps & Full-duplex, the link does come up and work. I have also tried disabling auto MDI-X, but that does not seem to change much either.

My question is what could be causing the link to only establish at 10 Mbps? I have attached some scope pics to help isolate the problem. The scopes are all from one of the RX/TX pairs between the switch and the AC coupling caps.

  • Scope 1) Forced 100 Mbps idle traffic
  • Scope 2) LCW from VDSL module (left burst), LCW from switch (right burst)
  • Scope 3) NLP (single burst of LCW) from VDSL module

Forced 100 Mbps idle traffic LCW from VDSL module (left burst), LCW from switch (right burst) NLP (single burst of LCW) from VDSL module

  • \$\begingroup\$ Try half-duplex in case of crosstalk. \$\endgroup\$ – Sunnyskyguy EE75 May 7 at 20:02
  • \$\begingroup\$ Have you impedance controlled the lines between the PHYs? Lets see pic of the layout \$\endgroup\$ – Voltage Spike May 7 at 20:11
  • 1
    \$\begingroup\$ Some output stages are not compatible. Some require external resistors as well. Some chips require changing their output drivers to act differently how they source and sink current (clasd A vs class B). In addition these may recommend disabling autonegotiation and just force the link to 100M and fullduplex, as 10M might require different capacitor values and/or biasing. 100nF caps have worked for me, with all the above tricks. \$\endgroup\$ – Justme May 7 at 20:24
  • \$\begingroup\$ examine photo #3, the fall time of the BLUE is 3/4 of a 50nanosec division, or 37 nanoseconds. Inverse of 37nS is 22MHz. \$\endgroup\$ – analogsystemsrf May 8 at 4:02
  • \$\begingroup\$ @analogsystemsrf What does the inverse fall time of the NLP have to do with the link speed achieved? \$\endgroup\$ – vix May 8 at 13:12

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