My first question is how does the drain voltage increase V(drain) when the source voltage V(source) is increased for the below common gate FET:
And secondly and most importantly in AC analysis they short the gate and Vdd to ground. What confuses me is that in AC small signal analysis of this circuit if we short the gate to ground(meaning that the FET is not biased), how come the FET current change? So in reality on a breadboard if I short the gate and Vdd to ground the MOSFET output will always be at ground level and the FET will be in cut off and will pass no signal at all. So I hope I could articulate my confusion here.