1
\$\begingroup\$

I'm implementing a priority queue on FPGA such that if some external signal is up (\$w_r\$) the priorities are evaluated and the priority queue us updated accordingly. The schematic is the following:

enter image description here

My approach is:

module priorityQueue(
input logic [13:0] dataIn,
input logic clk,
input logic wr,
output logic [7:0] out1,
output logic [7:0] out2
);

logic [13:0] dataInQueue [7:0];
logic [7:0] we;
bit [2:0] trigger = 0;



always_comb begin

for (int i = 0; i < 8; i++) 
    we[i] = (dataInQueue[i][13:8] < dataIn[13:8]);

if (we[7])
    trigger = 7;
else if (we[6])
    trigger = 6;
else if (we[5])
    trigger = 5;
else if (we[4])
    trigger = 4;
else if (we[3])
    trigger = 3;
else if (we[2])
    trigger = 2;
else if (we[1])
    trigger = 1;
else if (we[0])
    trigger = 0;  
end

always_ff @ (posedge clk)
    if (wr) begin
       dataInQueue[trigger] <= dataIn;
       case(trigger)
        3'b111: begin for (int i = 6; i < 0; i--)
                    dataInQueue[i] <= dataInQueue[i + 1];
                    end
        3'b110: begin for (int i = 5; i < 0; i--)
                      dataInQueue[i] <= dataInQueue[i + 1];
                      end
        3'b101: begin for (int i = 4; i < 0; i--)
                      dataInQueue[i] <= dataInQueue[i + 1];
                      end
        3'b100: begin for (int i = 3; i < 0; i--)
                      dataInQueue[i] <= dataInQueue[i + 1];
                      end
        3'b011: begin for (int i = 2; i < 0; i--)
                      dataInQueue[i] <= dataInQueue[i + 1];
                      end
         3'b010: begin for (int i = 1; i < 0; i--)
                      dataInQueue[i] <= dataInQueue[i + 1];
                      end
         3'b001: dataInQueue[0] <= dataInQueue[1];

        endcase
   out1 <= dataInQueue[7][7:0];
   out2 <= dataInQueue[6][7:0];

    end



endmodule

I'd like to focus on the always_ff part. Note that there a shift occurs depending on which \$w_e\$ was triggered. So, the shift depends on that factor. So far it seems to work, but is there a better to way to approach this in order to avoid redundancy?

note: the two "outs" are used only to visualize the queue in LEDS in the target.

\$\endgroup\$
0
\$\begingroup\$

I would definitely verify how the synthesis tool implements this that but here is my attempt at reducing the line number count:

always_ff @ (posedge clk)
if (wr) begin
   dataInQueue[trigger] <= dataIn;
   for(int i = 0; i < 7; i++) begin
      if (trigger > i) begin
         dataInQueue[i] <= dataInQueue[i + 1];
       end
    end
end
\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.