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I'm using a P-Channel (DMP1045UQ) and an N-Channel (BSS138K) FET to pull a 12v Logic line (12v @ 5mA) high (from GND) from a Logic Level(3.3v) MCU I/O pin.

Here is the schematic, where VIN = 12v, MCU_TEL_ON = MCU Pin and TEL_ON_IO is the line that is being pulled high. Schematic

My questions are:

  • Have I done anything egregious here?
  • Is R17 even necessary? Seems to work fine with it in the circuit, though.

Additionally, the circuit does not need to switch quickly -- TEL_ON_IO is meant to be kept high for long periods of time.

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Your PMOS gate must tolerate the entire swing of Vin. Do not assume that Vgs_max is the same as Vds_max because it does 0% of the time from what I've seen.

The PMOS you have chosen has Vds_max = 12V, but Vgs_max = 8V and you plan to have Vin = 12V which will blow your PMOS the first time you pull its gate low.

R17 is necessary to turn the PMOS off by discharging the gate capacitance since the NMOS can't do anything to turn the PMOS off on its own.

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  • \$\begingroup\$ Thanks! I also forgot to add a resistor from the NMOS gate to GND to discharge its gate. \$\endgroup\$ – t3ddftw May 10 at 20:25
  • \$\begingroup\$ Small follow-up the BSS54 would be a better PMOS choice, with a -20v Vgs, right? \$\endgroup\$ – t3ddftw May 10 at 20:43
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    \$\begingroup\$ @t3ddftw Yes. Just note it's resistance is 10 ohm which is rather high, but what you get in return is low gate charge so it will turn on faster. \$\endgroup\$ – DKNguyen May 10 at 22:01
  • \$\begingroup\$ RdsON is okay as long as it's less than ~1% of the load resistance, which in this case is 47 Ohms (given R18 @ 4.7k,) right? That's what I was basing my search on :) \$\endgroup\$ – t3ddftw May 10 at 22:17
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    \$\begingroup\$ Yeah, it's not a big deal in this case since you're just talking about a signal (almost no current) and it's small compared to the other resistors in the circuit. \$\endgroup\$ – DKNguyen May 10 at 23:03
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3 errors:

  1. Pch, DS is reversed
  2. Pch Vgs +/-8 max is exceeded
  3. Item 2 above is due to extremely low RdsOn 31mΩ which is a poor choice considering 4k7 load. Usually below 1% of load is adequate

err # 2 "could be fixed" with a series R divider.

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  • \$\begingroup\$ For #1, I don't think these are reversed. Should positive voltage not be applied to the "Source"? In my testing, if I connect PchD to +12v and PchS to my DMM, I always have at least 12v. With PchS to 12v and PchD to my DMM, I get 12v only when the NchG is pulled high. Thanks for pointing out the inadequacy of DMP1045UQ! \$\endgroup\$ – t3ddftw May 10 at 20:23
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    \$\begingroup\$ Yes but Diode is always conducting in Pch and source is on ground side. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 May 10 at 21:04
  • \$\begingroup\$ I realized the error of my schematic -- my source is what the diode is pointing towards. \$\endgroup\$ – t3ddftw May 10 at 21:48

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