For any design of an amplifier or OTA, we are given the specs which we need to achieve including:

  • Gain

  • UGBW or 3db BW

  • Slew rate

  • Power consumption

  • Phase Margin

  • Load capacitance

I would like to design a folded cascode using the gm/Id method. I was able to successfully get all the gm/Id curves for NMOS and PMOS for my technology node. I did that for a family of channel length (4 values). I got the following plots:

  • fT vs gm/Id

  • gm*ro (intrinsic gain) vs gm/Id

  • Id/W vs gm/Id

  • gm/Id vs Vov= (Vgs-Vth)

I also got the same plots vs Vov instead of gm/Id.

I am trying to understand, given these plots and given my specs, how to approach the design process. I have input transistors, current mirrors, and cascode transistors in my design.

My question is sort of general, how to design a cct using gm/Id method given the specs and the plots.

I found this flow diagram online but couldn't make sense out of it. A


1 Answer 1


I'm speaking from about a semester of experience in analog VLSI mostly focusing on amplifiers. I'm sure that industry experts might have other insight or better approaches, but what I've described has generally worked for me throughout my course, as a first-pass approach to get me close to where I need to be (or to determine that a set of specs might be infeasible so I can follow up with whoever set the specs). I've generally had to take a few iterations of tweaking values to get things to work right in simulation and post-layout.

Given a desired closed-loop gain and bandwidth, you can compute the necessary gain-bandwidth product of the amplifier. Then, under the assumption that the output pole is the dominant pole, you can easily use the gain-bandwidth product to set your system transconductance:

$$ \text{GBW} = \frac{G_m}{2\pi C_L}$$

When the dominant pole is associated with a different node, this becomes a bit more complex and depends on the exact nature of the pole and how that node is driven, but you might be able to still get a similar relation out. When using dominant pole compensation, you'll need to thoroughly look at your compensation scheme to determine a way of computing the system's gain-bandwidth product. For example, for the indirect compensation scheme we used for our operational amplifier design, described here, the GBW was given by \$\frac{g_{m,\text{stage1}}}{\mathbf{4}\pi C_C}\$, when the compensation pole was indeed the dominant pole1. Even though you might not be able to compute the actual phase margin here (since you don't know what the other poles are like) you can already relate \$C_C\$, \$g_m\$, and GBW to guide further decisions.

By looking at the folded cascode's small signal model, you can easily relate your transconductance requirement from the previous step to the transconductance of the input FETs; this allows you to select an inversion coefficient and bias current that are achievable given your technology and current limit.

Because you are working with a folded cascode, intrinsic gain isn't going to be a terribly meaningful value for working with the open-circuit voltage gain of the device, because the gain (\$G_mR_o\$) arises from a system transconductance term associated with the input branch of the folded cascode and a system output impedance mostly associated with the output branch and cascode.

You can then set your current mirrors and cascode transistors around your desired open-loop gain and output impedance. Because you have a folded cascode, you can set the current (and thus the corresponding transistor widths) on the output branch to be low in order to keep output impedance high. As an added benefit, this allows you to put more of your current budget toward transconductance on the input side.

The slew rate requirement is related to bias current values and the values of various capacitances (mainly compensation and load), since large-signal slew behavior is typically a product of charging or discharging a capacitor as fast as possible (i.e. with transistors fully cut off or in full triode). You'll want to consider a large-signal model of your circuit, as it responds to a sudden large step in the input (or for an op-amp/diff-amp, how it responds to a massive difference in the two inputs). Consider both positive and negative slews separately (since you will likely have different charge/discharge paths for your load and/or compensation capacitors). This will set your limit on compensation capacitor values, going hand-in-hand with system current. You may find that your previous unity gain frequency was tied to a too-slow slew rate, and that you need an overdesign on small-signal AC specs to reach an acceptable slew rate.

Once you have a rough limit on allowable cap values, you can consider sweeps of the capacitor value, allowing you to hone in on the specs that you need to reach, unless your methodology has an analytical way of computing the necessary compensation capacitor given required phase margin and such; mine did not so I resorted to sweeps to set the compensation capacitor.

1 The choice of compensation scheme itself will affect things. Depending on your professor's school of thought you might be asked or required to use a Miller capacitor for compensation rather than indirect compensation. Miller capacitors introduce their own problems such as feed-through (meaning a zero in the \$s\$-plane) which complicate the analysis, and they often cause lower slew rates; I thus focus on indirect compensation for my example.

  • 1
    \$\begingroup\$ Thanks for the detailed answer! This definitely helped. You mentioned closed and open loop gains. Would you shade some light on the test benches configuration while testing for each of the specs (Gain, BW, Slew Rate, Power Consumption..) \$\endgroup\$
    – HaneenSu
    May 10, 2019 at 23:08
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    \$\begingroup\$ @HaneenSu I don't have any particular insight on the testbenches themselves; gain/BW are straightforward AC analyses on the closed-loop system with feedback; open-loop gain can be derived from your toolkit's stability tools (e.g. Cadence's stb and the related probes), slew rate comes from some transient analyses, and power consumption can be a direct measurement of current into your VDD pin. Please let me know if there is anything further I can clarify. \$\endgroup\$
    – nanofarad
    May 10, 2019 at 23:32
  • \$\begingroup\$ Thanks for your prompt response and insight Andrey. For the gain/BW AC analysis, do we form the feedback by just shorting the output with one of the two inputs of the differential input pairs? \$\endgroup\$
    – HaneenSu
    May 10, 2019 at 23:37
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    \$\begingroup\$ @HaneenSu It depends on what your desired outcome is since it's not 100% clear what kind of amplifier we have in mind. If you're making an op-amp and want it to operate in unity gain, you'd short the output to the inverting input. If you're making a fully differential amplifier you'd need a different feedback setup depending on the desired gain. \$\endgroup\$
    – nanofarad
    May 10, 2019 at 23:41
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    \$\begingroup\$ @HaneenSu If you're only interested in open-loop gain you can connect it in unity gain feedback and run a stability analysis (which will give you loop gain and phase margin). Because unity gain has feedback network gain = 1, loopgain is the same as open-loop gain in this case. Are you using Cadence by any chance? (if so you can run an stb analysis with an analogLib:iprobe inserted on the feedback path to analyze the feedback loop). If you're using some other toolset you'll need to consult your documentation. \$\endgroup\$
    – nanofarad
    May 11, 2019 at 0:18

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