I'm speaking from about a semester of experience in analog VLSI mostly focusing on amplifiers. I'm sure that industry experts might have other insight or better approaches, but what I've described has generally worked for me throughout my course, as a first-pass approach to get me close to where I need to be (or to determine that a set of specs might be infeasible so I can follow up with whoever set the specs). I've generally had to take a few iterations of tweaking values to get things to work right in simulation and post-layout.
Given a desired closed-loop gain and bandwidth, you can compute the necessary gain-bandwidth product of the amplifier. Then, under the assumption that the output pole is the dominant pole, you can easily use the gain-bandwidth product to set your system transconductance:
$$ \text{GBW} = \frac{G_m}{2\pi C_L}$$
When the dominant pole is associated with a different node, this becomes a bit more complex and depends on the exact nature of the pole and how that node is driven, but you might be able to still get a similar relation out. When using dominant pole compensation, you'll need to thoroughly look at your compensation scheme to determine a way of computing the system's gain-bandwidth product. For example, for the indirect compensation scheme we used for our operational amplifier design, described here, the GBW was given by \$\frac{g_{m,\text{stage1}}}{\mathbf{4}\pi C_C}\$, when the compensation pole was indeed the dominant pole1. Even though you might not be able to compute the actual phase margin here (since you don't know what the other poles are like) you can already relate \$C_C\$, \$g_m\$, and GBW to guide further decisions.
By looking at the folded cascode's small signal model, you can easily relate your transconductance requirement from the previous step to the transconductance of the input FETs; this allows you to select an inversion coefficient and bias current that are achievable given your technology and current limit.
Because you are working with a folded cascode, intrinsic gain isn't going to be a terribly meaningful value for working with the open-circuit voltage gain of the device, because the gain (\$G_mR_o\$) arises from a system transconductance term associated with the input branch of the folded cascode and a system output impedance mostly associated with the output branch and cascode.
You can then set your current mirrors and cascode transistors around your desired open-loop gain and output impedance. Because you have a folded cascode, you can set the current (and thus the corresponding transistor widths) on the output branch to be low in order to keep output impedance high. As an added benefit, this allows you to put more of your current budget toward transconductance on the input side.
The slew rate requirement is related to bias current values and the values of various capacitances (mainly compensation and load), since large-signal slew behavior is typically a product of charging or discharging a capacitor as fast as possible (i.e. with transistors fully cut off or in full triode). You'll want to consider a large-signal model of your circuit, as it responds to a sudden large step in the input (or for an op-amp/diff-amp, how it responds to a massive difference in the two inputs). Consider both positive and negative slews separately (since you will likely have different charge/discharge paths for your load and/or compensation capacitors). This will set your limit on compensation capacitor values, going hand-in-hand with system current. You may find that your previous unity gain frequency was tied to a too-slow slew rate, and that you need an overdesign on small-signal AC specs to reach an acceptable slew rate.
Once you have a rough limit on allowable cap values, you can consider sweeps of the capacitor value, allowing you to hone in on the specs that you need to reach, unless your methodology has an analytical way of computing the necessary compensation capacitor given required phase margin and such; mine did not so I resorted to sweeps to set the compensation capacitor.
1 The choice of compensation scheme itself will affect things. Depending on your professor's school of thought you might be asked or required to use a Miller capacitor for compensation rather than indirect compensation. Miller capacitors introduce their own problems such as feed-through (meaning a zero in the \$s\$-plane) which complicate the analysis, and they often cause lower slew rates; I thus focus on indirect compensation for my example.
