Picture to Keep the Terminology Clear


I am in the plan of using ETH for inter processor communication

I need few ETH lanes to be shared between boards, i wish to avoid ETH PHY and magnetics as the interface is between two processors only.

I have few RGMII outputs coming from a TI-TDA2x which needs to be taken to a back-plane,from back plane i shall take it another board having TI-TDA2x

i want to know what is the maximum safe distance between MAC to PHY to be maintained ?

TI-TDA2X Datasheet

My Speed Requirement : 1 Gbps


Without reading the datasheet, 1Gigabit is 1 nanosecond. On FR-4, with Er of about 4, the 1_foot in air becomes about 1/2_foot in epoxy-fiberglass combined with air above. You may need to tolerate round trip reflections and/or ISI energy stored in the IC leadframe and bondwires and PCB vias and Silicon ESD non-linear capacitances. Thus round trip will be 1/4 foot per side, or 3" (7.5 cm). If the link has adaptive equalization, life should be very good.

  • 1
    \$\begingroup\$ 1) 1000BASE-T isn't 1 GHz; between scrambling, multilevel signalling, and multiple lanes, the signal rate is 125 Mbaud. 2) But the OP isn't asking about that, they're asking about the RGMII signalling, which is a different beast altogether. And it's not clear how the round-trip time of a signal is supposed to equate to its maximum distance… \$\endgroup\$ – duskwuff May 11 at 7:33
  • \$\begingroup\$ GMII interface operates at 125MHz, RGMII also has 125MHz clock but operate on both clock edges for double data rate. Perhaps the real question is whether the chips are even able to work in a mode where RGMII MACs are wired together in a cross-over fashion. Check datasheets and support forums first if you need a PHY. Two PHYs are easier to connect together without magnetics. \$\endgroup\$ – Justme May 11 at 9:01

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