I have some misunderstanding about what clock cycle really is. I generally understand a schema how CPU processes an instruction. Intel manual describes the schema for Intel NetBurst architecture as
• Prefetches instructions that are likely to be executed
• Fetches instructions that have not already been prefetched
• Decodes instructions into micro-operations
• Generates microcode for complex instructions and special-purpose code
• Delivers decoded instructions from the execution trace cache
So execution of single instruction involves pretty much of work from front end. Then goes uops executing by out of order backend and then instruction is being retired.
Looking at Agner Fog instruction latency https://www.agner.org/optimize/ we have that
add x86 instruction requires 1 core clock cycle. I don't understand how all this front end, backend and retirement job fit in a single clock cycle.