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I have some misunderstanding about what clock cycle really is. I generally understand a schema how CPU processes an instruction. Intel manual describes the schema for Intel NetBurst architecture as

• Prefetches instructions that are likely to be executed

• Fetches instructions that have not already been prefetched

• Decodes instructions into micro-operations

• Generates microcode for complex instructions and special-purpose code

• Delivers decoded instructions from the execution trace cache

So execution of single instruction involves pretty much of work from front end. Then goes uops executing by out of order backend and then instruction is being retired.

Looking at Agner Fog instruction latency https://www.agner.org/optimize/ we have that add x86 instruction requires 1 core clock cycle. I don't understand how all this front end, backend and retirement job fit in a single clock cycle.

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    \$\begingroup\$ I worked on the P II. In that case, for example, there was a 32-byte buffer used, in parallel, by a section that decodes up to three instructions in 1 clock, placing the resulting microops (RISC instructions, really) into the ROB (re-order buffer.) But while that is going on, other sections in the CPU are performing other tasks, such as the retire-unit retiring up to three RISC instructions per clock, as well. \$\endgroup\$ – jonk May 11 at 23:07
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The five bullet points you mention happen simultaneously, executed by the different units of the CPU.

They are just "triggered" by the clock cycle; then they reserve that unit for as long as they take. Most of these operations just take one cycle, so that the every clock cycle the whole processing pipeline "moves one step forward".

But, for example, if an operation (e.g. fetching from RAM) takes multiple cycles, that part of the processor simply is blocked for that long. The others will, in the meantime, continue to do their work – as far as that isn't blocked by the blocked unit.

In your case, the add instruction simply takes one cycle to execute; it will have taken multiple cycles to be fetched from RAM, a cycle to be decoded.

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