I am currently trying to reduce the offset voltage of the circuit attached below to less than +/- 2mV over a 1V to 4V input range.

I have a few constraints for this task:

  • I can use nmos, pmos and pmos4 but can't use nmos4 as the fabrication process does not support separate bulks for NMOS transistors.

  • I cannot use controlled sources e.g (vcvs,vccs,ccvs,cccs) except when calculating Voffset

  • I can only use one Vdc for Vdd and one Vdc for Vin and use only idc for biasing

  • Use at least 100nA bias current in all transistors

So far I have tried adding cascodes to the circuit to reduce this offset voltage but no luck. I would really appreciate it if someone could point me in the right direction regarding this task. Thank you.

Voltage Follower Circuit:



Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Browse other questions tagged or ask your own question.