I am currently trying to reduce the offset voltage of the circuit attached below to less than +/- 2mV over a 1V to 4V input range.
I have a few constraints for this task:
I can use
pmos4but can't use
nmos4as the fabrication process does not support separate bulks for NMOS transistors.
I cannot use controlled sources e.g (
cccs) except when calculating Voffset
I can only use one
Vinand use only
Use at least 100nA bias current in all transistors
So far I have tried adding cascodes to the circuit to reduce this offset voltage but no luck. I would really appreciate it if someone could point me in the right direction regarding this task. Thank you.
Voltage Follower Circuit: