I want to make a clock generator for Altera EPM240T100C5N using the CPLD itself as a Pierce oscillator. This CPLD has Schmitt trigger inputs so I guess this should be possible. What I`m not sure about is the reliability of this approach. Can I use a CPLD inverter to build an oscillator? If yes, how much influence will the supplied voltage have on the resulting jitter? Will there be much difference between 2.5V and 1.8V at 48 MHz?
I do not recommend this approach. You may get some circuit to oscillate under some conditions but you may very well have problems with jitter, unreliable startup and off frequency operation.
You should instead use a ready made crystal oscillator part. These days these are very small parts and can be placed near to the FPGA. The oscillator application only requires a bypass capacitor across its power pins and for some applications a small value series termination resistor at the oscillator may be required.
This CPLD has Schmitt trigger inputs so I guess this should be possible.
Actually, if it has Schmitt trigger inputs it makes it impossible. A Schmitt trigger would just about guarantee that the oscillator would start up in a mode that excites the RC components of the circuits and bypasses the crystal altogether.