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Is it possible for a slave to initiate communication in SPI?

I thought due to the chip select i.e. NSS feature only master can communicate the communication. However, in I2C, the slave can also initiate communication by changing the RW flag in the i2c communication. Is this correct?

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    \$\begingroup\$ Just to add to existing answers, common approach to this would be to use a separate GPIO pin as an interrupt which signals to the master than the slave has data read to be read. \$\endgroup\$ – scotty3785 May 13 at 8:08
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    \$\begingroup\$ @Prawn_Hongs can you clarify what you mean by 'initiate'? I think you might be getting confused with master/slave reading/writing data. \$\endgroup\$ – pm101 May 13 at 9:11
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With both only master can initiate the communication. I²C can however have multiple masters and the nodes can change the roles, so it is a bit more flexible. But saying that slave could initiate communication is still not correct.

A common way for a slave to indicate that it wants to communicate to the master is to use an interrupt signal. On many sensors and ADCs they are called "data ready" or something similar. After a slave has asserted the signal the master knows that the slave has some new data available.

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Both SPI and I2C only allow the master to initial communication. However, it is possible for slave devices to indicate that something has happened which merits communicating with them via an interrupt pin.

Interrupt pins are fairly common on ICs with serial busses. The pin changes state to indicate that some event has occurred, and the master can then watch to pin to know when it should communicate with the slave to find out what happened.

Even in that case though, it's up to the master to start the communication and it can simply ignore the slave if it wants to.

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No, in I2C only the master can start communicating on the bus, and all slaves must follow the master. A slave can't initiate communication and specifically the slave can't change the RW flag in any way.

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With SPI, the MOSI line always transmits data from the master to the slave, and the MISO line always transmits data from the slave to the master.

With I²C, there is only a single data line for both direction. The R/W bit controls which device transmits data bytes and with device transmits the ACK bits, but the R/W bit itself is always controlled by the master. (The R/W bit can be changed with a repeated start condition, but only by the master.)

And the clock is always controlled by the master. (An I²C slave can delay clock cycles with clock stretching, but it cannot generate new clock cycles.)

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In SPI, each device has a fixed role as master or slave. In I2C, the roles of devices can change dynamically. Any device which initiates a transaction on the bus (as opposed to soliciting a transaction via some means outside the bus) must behave as master for that transaction, but that device could behave as slave for transactions initiated by other devices. Except for a couple of details, I2C is predicated on there being exactly one master and one slave for any particular transaction:

  1. When using longer addressing formats, multiple devices can act tentatively as slaves while awaiting their full address. In that state, the only thing slaves can do is indicate to the master that the slave the master is interested in might be ready to respond.

  2. Multiple devices may act simultaneously as masters if all want to send the same data at the same time. This may potentially cause trouble if e.g. two devices each request that a device increment a counter and then simultaneously request that the device decrement it. If the two masters send bit-for-bit identical requests, neither one would lose arbitration, and thus each would think that its request was honored.

Most I2C systems contain only one device that can ever act as master, but the protocol would allow for multiple devices. Unless a bus is expected to have multiple masters, however, it's easier to implement a device that expects to be the only master than one which can co-exist with other masters on the bus.

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  • \$\begingroup\$ How does bus arbitration work with I2C? Don't I2C peripherals on MCUs transmit blindly without listening for collisions? \$\endgroup\$ – Navin May 14 at 1:46
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    \$\begingroup\$ @Navin: Any device that sees a falling edge on SCL is required to hold SCL low until it has determined what, if anything, it needs to do with SDA, and each time the master releases SCL it is required to wait until it actually goes high (everyone has released it) before proceeding. If two masters simultaneously create start conditions, each may think it has the bus (whichever one is faster would wait for the other to release SCL after each bit) until one tries to transmit a 1 and the other a 0, at which point the 0 would win and the device that tried to transmit a 1 would drop off the bus. \$\endgroup\$ – supercat May 14 at 14:58

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