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Let a be input value, k1 and k2 be two keys. Then

 X=(a+k1) mod m;
 X=(x<<4);
 Y=x^k2;

Can i decrypt back? Because i am not getting exact answer while decrypting. How to rotate bits in verilog? Can you please help with code if this possible?

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migration rejected from crypto.stackexchange.com 2 days ago

This question came from our site for software developers, mathematicians and others interested in cryptography. Votes, comments, and answers are locked due to the question being closed here, but it may be eligible for editing and reopening on the site where it originated.

put on hold as off-topic by duskwuff, RoyC, Warren Hill, Finbarr, Dave Tweed 2 days ago

  • This question does not appear to be about electronics design within the scope defined in the help center.
If this question can be reworded to fit the rules in the help center, please edit the question.

  • \$\begingroup\$ Welcome to crypto.stackexchange - This appears to be a question for the electrical engineering stackexchange. I will migrate this there for you. The relation to cryptography is not obvious and does not seem important to the question, so I recommend editing it to ask about arithmetic and bit shifts without mentioning cryptography. \$\endgroup\$ – Ella Rose May 15 at 17:39
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    \$\begingroup\$ Despite comments to the contrary, this is not primarily a question about electrical engineering. This question should not have been migrated. \$\endgroup\$ – duskwuff May 15 at 19:08
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I might be wrong, but I do not think that you will be able to decrypt it. You are setting the first X to a remainder so there is no way to guarantee that you get the original value back. For example, assuming k1 is a positive value, and we set m = 2, then X has 2 possible values, 0 and 1. If the first X is 0, and a = 1, than k1 can be any odd number

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  • \$\begingroup\$ Actually i was able to decrypt back when i was using only modular addition and bit wise exor opeartion. After adding shift, only few values are decrypting back. Others not! \$\endgroup\$ – SHRIVATHSA TUNGA May 16 at 0:43
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I leave the decryption question to somebody else, but how to rotate a vector in Verilog:

reg [7:0] rotate_me;
always @( posedge clk) 
   rotate_me <= {rotate_me[6:0],rotate_me[7]};
 // or in the opposite direction:
   rotate_me <= {rotate_me[0],rotate_me[7:1]};
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