What you have looks pretty good to me.
However, when I'm making the first version of a circuit, I like to add in some flexibility in case the design needs tweaks, or something external changes.
I would suggest (if you have some extra PCB space):
- Connect all unused pins to separate through-hole test points. This allows you to connect a wire later-on if you decide that you need to use them for something.
- Add an unpopulated resistor from INT (Pin12) to an unconnected through-hole pad. This will allow you to configure the INT as open-drain if you decide totem-pole (push-pull) isn't working for you. You could then apply the voltage of your choice to the unconnected pad (as log as it's less than Vdd), and add a conveniently-sized pull-up resistor.
- Add a zero-ohm resistor (jumper) from FSYNC to GND (in case you would like to use its functionality in the future).
- Keep traces for CPOUT and REGOUT short, and ground the caps using short fat traces . Keep the 'loop area' of these nets as small as possible to reduced possible generated emi. Do not share these ground traces with other parts of the circuit (connect the ground connections of these caps directly to your main ground plane, as close to the chip's ground pins as possible).
- Their reference design shows a 10nF cap on the VLOGIC pin. You will have separate connections for VDD and VLOGIC, so you might as well (you should) have dedicated caps near each power pin for supply bypassing.
Keep an eye on the diagram for power-on sequencing in section 7.4. This shows that Vlogic must always be <= Vdd (it can't come 'on' first). Be sure this doesn't happen as your design evolves. Shorting Vdd to Vlogic, as you have it shown, should be fine (as the datasheet says that the time difference for power-up can be =0).
Show the PCB when your ready, for some more arm-chair review...