how to isolate coupled noise source in parasitic capacitance in high voltage pcb design?

I'm new designing a high/medium voltage (V <=10kV) with low voltage and low current (10mA). There will be only a few HV relays. Their coils will be triggered by LV.

I have read some literature about this subject. I have known that noise could be coupled to the parasitic capacitance at the insulation: "If noise couples through parasitic capacitance on the board or in the insulation, it can easily propagate to very sensitive areas of the board".

So, it could be bad news if this capacitor discharges its own charge and starts having continuity between 2 isolated points where should be isolation.

How could I avoid these capacitor effects? How can I stop the noise running through Capacitance between 2 isolated (or potential different) points?

• Don't overlap planes that are supposed to be isolated. Use common mode filters/chokes, and give the return currents a path of lower impedance than the isolation capacitance to flow through May 16, 2019 at 15:52
• Elecrtric fields go everywhere, unless your sensitive circuit in totally surrounded by metal. Lower impedances are less vulnerable. Metal pieces ABOVE the sensitive circuits will mostly shield, but not totally, because the electric field will enter at the sides. And slower changes in your highvoltages will induce smaller currents in your sensitive circuits. May 16, 2019 at 16:39

Parasitic capacitance is created whenever there are two conductors. The capacitance can be estimated with capacitance calculators. Parasitic capacitance values on PCB's typically exist in the pF range for traces and planes. Large plane to plane capacitance can be in the 100pF range (a 1000mm^2 has roughly 150pF of capacitance between planes).

Usually plane to plane capacitance can be used to your advantage in low voltage sections of a PCB. A ground plane can act like a bypass capacitor (with values of a few pF) which will cut out very high frequencies.

If you don't want these capacitave effects, then don't place traces or planes adjacent to each other. You wont' be able to eliminate capacitance entirely, but it is easy to make the values negligible.

You probably already know this already but I'll include it for anyone else with the same question:

With high voltage you need to consider creepage and clearance between traces, and at 10kV also the breakdown dielectric voltage of PCB. High voltage can arc between traces, so proper distance needs to be placed between them. Here is a calculator for distance.

It might be wise to build the board out of something other than FR4 with such high voltages on the board. Follow the guidelines here

• Thank you @laptop2d this is the guide I have been reading. I' m sure about not using FR4. But I did not find there any reference to the clearence between traces in HV, this calculator is a good tool that I need. There is another thing in that doc that is not explained. Where the gradient E and factor of E utilization must be calculated, and what to do with the results -or how to apply them- at pcb design. But I still looking for more information, I' ve just started with this. May 17, 2019 at 6:35
• Instead of saying thanks, upvote and if the question is answered then mark it meta.stackexchange.com/questions/126180/… May 17, 2019 at 15:40
• I would really like to do it but I have not earned the vote up privilege since now. Now you got the mark. May 20, 2019 at 7:32