I'm designing a board (with KiCAD 5.1.0) besides other I need to properly route two ethernet ports and the whole board should be kept as small as possible (50x82mm). The guidelines of components (magnetics) give some hint about trace layout but the main component (where the two ports originate) is not very well documented... anyway I looked around and did my best. The final result lead me to some question:

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On this port I had to reverse the magnetics ports to avoid vias and complex traces to connect the main component with magnetic IC itself:

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Please note that the ethernet connector is not an RJ45 since I have very big space constraints and RJ45 should not fit in the assembly.

In the first port I needed to reverse the polarity of the magnetic input for the same reasons as above:

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The effect of these workarounds are negligible on the overall performance? Take into account that both ethernet ports will be connected to a very near device (around 20cm of cable length or less) and that the overall troughput on such ports will never exceed 10Mbits.

Differential pairs have been setup to have 100ohm impedance (the board will have a standard 4 layer FR4 stackup).

To keep everything small and avoid complex traces I placed some of the passive components on the top layer and some other on the bottom side:

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Of course I needed to place some vias on the forbidden zone below the magnetic IC... is it soooo wrong?

Magnetics IC = Wurth 749010310.

Any comment will be appreciated. Of course I can share the whole design if someome wish/need to investigate further.


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