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I'm working with a Sierra Wireless BC127 (Bluetooth Module) I2S master which is generating Left-Justified, 16 bps @ 44.1khz sample rate. The Bit clock is set to 2.822 Mhz.

I want to use a Cirrus Logic WM8804 to convert the I2S data to S/PDIF @ 44.1khz (please ignore the fact that the BC127 can output S/PDIF -- I need both digital audio formats). It appears that since the WM8804 needs to operate in slave I2S mode, the internal PLL cannot be used to generate the clock, and MCLK must be provided.

Unfortunately, the BC127 does not output MCLK, so I believe I need to use the bit clock (BCLK) from the BC127 to generate MCLK.

  • I believe I can use something like the Cirrus CS2300-03 to generate the MCLK, is that correct?

  • If the above is correct, what should I multiply BCLK by in order to generate a useful MCLK?

  • Are there any simpler means of generating MCLK? Keep in mind that the BC127 won't run as an I2S slave.

  • Additionally, what frequency crystal should I connect to the WM8804 to generate the required S/PDIF signal?

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    \$\begingroup\$ Wouldn't it be simpler to have your bluetooth module output SPDIF, then use the WM8804 to decode this into I2S? You'd get both SPDIF and I2S outputs as desired. \$\endgroup\$ – peufeu May 17 at 23:12
  • \$\begingroup\$ @peufeu - that's a perfect solution. I totally had my blinders on and didn't stop to think that the BC can feed the SPDIF to the WM8804... Thanks! \$\endgroup\$ – t3ddftw May 18 at 0:37
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Reposting the answer I put in a comment:

I want to use a Cirrus Logic WM8804 to convert the I2S data to S/PDIF @ 44.1khz (please ignore the fact that the BC127 can output S/PDIF -- I need both digital audio formats)

Wouldn't it be simpler to have your bluetooth module output SPDIF, then use the WM8804 to decode this into I2S? You'd get both SPDIF and I2S outputs as desired.

Now that you confirmed it is possible, here's more:

If you need I2S, I presume you'll use this to feed a DAC chip. W8804 will decode SPDIF from your bluetooth module and generate I2S and MCLK from it. I don't remember the exact settings, but you can configure it to generate the MCLK frequency your DAC chip needs.

WM8804 is also very good at cleaning up jitter, so the I2S it generates could be cleaner that what comes out of the bluetooth module (although you'd have to measure it to be sure).

It can also act as a SPDIF pass-through, so you can route the SPDIF signal from the Bluetooth module, through the W8804, and then to the SPDIF output. If you have another I2S source, you can use W8804 as a mux and SPDIF encoder to output the source you want. It will also clean up the jitter on the SPDIF, although that's not very useful (clean clock recovery is better done on the receiving side).

If you use WM8804 to generate MCLK for a DAC, then I'd recommend using a XO instead of a crystal. The layout for WM8804 crystal oscillator is really difficult to get right, and I always got lower jitter with a sub-$1 XO.

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  • \$\begingroup\$ I know it's been a while since you answered this, but the WM8804 explicitly states that using a CMOS XO is not recommended for use with the PLL. Could you speak to which XO you're using that performs well? \$\endgroup\$ – t3ddftw Jun 28 at 21:44
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If I need a stable external clock source, and I'm not concerned about price. I usually use an XO CMOS output oscillator. Supply it with 3.3V and it gives you a clock out for the MCLK (in the datahseet the MCLK timing indicates that the MCLK can be set on Xin pin) .

There are many different frequencies available

enter image description here
Source: https://www.digikey.com/products/en/crystals-oscillators-resonators/oscillators/172?k=XTAL+OSC+XO+CMOS+SMD&k=&pkeyword=XTAL+OSC+XO+CMOS+SMD&sv=0&pv2150=u44.1MHz&sf=0&FV=ffe000ac&quantity=&ColumnSort=0&page=1&pageSize=250

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  • \$\begingroup\$ Thanks! Don't I need to base the MCLK on the BCLK? Otherwise, won't the clocks be out of phase and/or sync? \$\endgroup\$ – t3ddftw May 17 at 20:03
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    \$\begingroup\$ Doesn't look like it: Check out the bottom paragraph on pg 44. The biggest clue is the statement "BCLK is also generated by the WM8044", and "BCLK = MCLK/4" if you like the answer, upvote instead of saying thanks: meta.stackexchange.com/questions/126180/… \$\endgroup\$ – Voltage Spike May 17 at 20:15
  • \$\begingroup\$ Apologies, thought I had upvoted. In either case, paragraph 3 on pg 44 states that in slave mode, LRCK and BCLK are inputs, which implies that the WM8804 won't generate BCLK/MCLK in that configuration. \$\endgroup\$ – t3ddftw May 17 at 20:30

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