0
\$\begingroup\$

When one bit information is transferred between two different clock domains, we use 2 Flip-flops or double synchronizers. But when we transfer multi bit signals across two different clock domains, why is it that, just double synchronizers alone aren't sufficient? Why is it that in this case we need special hand shake signals/ gray code etc along with the double synchronizing flip-flops that complicates the entire setup?

\$\endgroup\$
  • \$\begingroup\$ Multiple bits implies a bit rate and, if this bit rate is not sufficiently synchronized (by some means) then eventually there will be errors either receiving too many bits or missing bits. \$\endgroup\$ – Andy aka May 20 at 7:58
  • \$\begingroup\$ Assuming that we are talking about buses: There are plenty of resources around regarding clock domain crossing, metastability and its implications. So is there something specific regarding this topic and existing explanations which is unclear or did you just lack the right search terms? Some resources explain nicely that even double synchronizer typically only reduce the chances to get struck by a metastability but it still can happen. Or is it maybe unclear that cdc actually implies at not all signals crossing behave the same/might show different delay and stability characteristic? \$\endgroup\$ – Christian B. May 20 at 9:22
3
\$\begingroup\$

Transferring a single bit is simple. It has only two states, and when a transition occurs, it can only be either in the previous state or the new state. Therefore the ONLY concern is metastability, and the two-flop synchronizer is normally sufficient to address this issue.

However, a multi-bit bus has an additional issue — when crossing a clock domain boundary, different bits might be perceived as changing on different clock edges because of tiny differences in delays in the logic and in the wiring. Some bits might go metastable while others won't, and they might take different amounts of time to resolve themselves. Now you don't have just the previous state and the next state — you can have any number of intermediate states in which only some of the bits have their new values, and some of the bits still have their old values.

This additional issue of data coherence is why the additional handshake logic is required. And this is why the dual-clock or asynchronous FIFO is a key building block in digital systems that involve multiple clock domains — it collects all of the required elements together into one neat package.

\$\endgroup\$
  • \$\begingroup\$ That's a good explanation. Adding to Dave's answer, now even after using the FIFO mechanism for payloads, the pointer (for the depth of the FIFO) still could be a multi-bit signal and the write pointer (sending clock domain) needs to be synchronized into reading/ receiving clock domain. And this is where Gray code is useful where every transition (or increment) is represented by a single bit change. This way the handshake can be reduced to the problem of synchronizing (metastability concern and NOT data coherence concern) a two state change as mentioned in the first part of this answer. \$\endgroup\$ – Rajesh S May 21 at 10:59
  • \$\begingroup\$ @RajeshS: All of that is built into the 2-clock asynchronous FIFO. There is a discussion about Gray code specifically here. \$\endgroup\$ – Dave Tweed May 21 at 11:05

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.