5
\$\begingroup\$

Some micros have all bits of a port nicely lined up, while others' bits seem to have been scattered by the winds to all four points of the compass. Why?

\$\endgroup\$
  • \$\begingroup\$ I am thinking about the interesting and cheaptastic LPC1* ARM chips. They only put 3 or 4 bits max per port in a row. \$\endgroup\$ – joeforker Sep 14 '10 at 20:00
5
\$\begingroup\$

I occasionally do chip design - as mentioned above many chips will intersperse power and grounds within parallel buses so that the drivers will have enough power (lead inductance is an issue - plus you don't want to starve the core when driving external loads).

However there are other issues - you might be constrained for on-die routing resources meaning it makes more sense to push those issues externally - I worked on a PCI interface where we tried hard to push pins to the right places (total system cost means getting to a 4 layer board can be important) but were constrained in some critical timing paths that meant we had to push some of the timing budget off-chip by moving the pads closer to the rest of the logic they drove while assuming longer external traces

Sometimes you design a die but it goes into multiple packages - maybe the BGA package is optimally pinned out but not the QFP - or maybe the package was chosen late in the design cycle after the pads on the die were already chosen

So there's lots of reasons - sometimes it really is that the chip designer didn't think ahead

But remember for some buses you don't always have to wire up all pins exactly - if you're wiring up a SRAM/DRAM (or sometimes even flash if it's not being pre-loaded) you can often switch bits within a byte or even (carefully! depends on the chip) address bits

\$\endgroup\$
6
\$\begingroup\$

Often this has alot to do with lead inductance. You need to keep your grounds spread out, and based on layout decisions in the chip internal to the package it may need to spread out the I/O pins.

Would you rather have ground problems or spread out pins. In general, I use #define to handle which pin I am using and all but forget which actual pin it is. Since most people do this also, chip manufacturers know this and focus on electrical parameters.

\$\endgroup\$
  • 1
    \$\begingroup\$ I don't think the question was referring to having a few grounds. It read scattered by the winds to all four points of the compass. Also, while programmers don't have to worry about it after they import the header, I think that the bigger problem would be in the layout of the PCB. \$\endgroup\$ – Kevin Vermeer Sep 14 '10 at 17:51
  • \$\begingroup\$ The fact that you have to spread apart your grounds has an effect on the placement of all pins. There is also a lot to do with how the chip was designed at the gate level. When you look at chip designs like this vega.unitbv.ro/~nicula/vlsi/layout.html you might be able to begin to see how it could be hard to put pins in order by their port \$\endgroup\$ – Kellenjb Sep 14 '10 at 18:47
  • \$\begingroup\$ @reemrevnivek, Yes, I understand that they are scattered, but why does that affect your layout. There should be Digital I/O almost everywhere. If you have a D- and a D+ for USB on a chip they are normally close for impedance reasons. But if it is general I/O you should know you can swap one Digital I/O to almost any other Digital I/O. decent layout/schematic suites allow you to mark pins as swappable. That way the layout runs smoothly. \$\endgroup\$ – Kortuk Sep 14 '10 at 19:45
3
\$\begingroup\$

Might have something to do with the alternate uses for a pin. If you have an oscillator connection then it would be a good idea to have it kept away from high-noise paths for instance.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.