Some micros have all bits of a port nicely lined up, while others' bits seem to have been scattered by the winds to all four points of the compass. Why?
I occasionally do chip design - as mentioned above many chips will intersperse power and grounds within parallel buses so that the drivers will have enough power (lead inductance is an issue - plus you don't want to starve the core when driving external loads).
However there are other issues - you might be constrained for on-die routing resources meaning it makes more sense to push those issues externally - I worked on a PCI interface where we tried hard to push pins to the right places (total system cost means getting to a 4 layer board can be important) but were constrained in some critical timing paths that meant we had to push some of the timing budget off-chip by moving the pads closer to the rest of the logic they drove while assuming longer external traces
Sometimes you design a die but it goes into multiple packages - maybe the BGA package is optimally pinned out but not the QFP - or maybe the package was chosen late in the design cycle after the pads on the die were already chosen
So there's lots of reasons - sometimes it really is that the chip designer didn't think ahead
But remember for some buses you don't always have to wire up all pins exactly - if you're wiring up a SRAM/DRAM (or sometimes even flash if it's not being pre-loaded) you can often switch bits within a byte or even (carefully! depends on the chip) address bits
Often this has alot to do with lead inductance. You need to keep your grounds spread out, and based on layout decisions in the chip internal to the package it may need to spread out the I/O pins.
Would you rather have ground problems or spread out pins. In general, I use #define to handle which pin I am using and all but forget which actual pin it is. Since most people do this also, chip manufacturers know this and focus on electrical parameters.