I am working on a design which area is an important factor to consider using:
- Synthesis tool: Synopsys design_vision
- Language: VHDL
lets explain my problem using two scenarios:
The main design is divided into a few sub-blocks. for example L1 is a sub-block of main design which is responsible to separate input vector to some smaller internal vectors. So, L1 is instantiated as a component into main design, L1 gets the input vector and separates it into sub-vectors. synthesis tool is putting buffer on every input bit coming to L1 (which is simply just a signal rewiring from main block to L1)
Overall area becomes e.g., say 50 um2 which 30 um2 is L1 block area
The main design is implemented into one flat block. for example L1 here is implemented as a process inside the main flat block and is responsible to separate input vector to some smaller vectors. So, L1 process gets the input vector in its sensitivity list and separates it into sub-vectors which are all internal signals . synthesis tool does not buffer every input bit.
Overall area becomes lets say 30 um2 and in comparison to Scenario1 it has 20 um2 less because of no buffer insertion.
It is important to note that the buffered net in Scenarion1 is non-clock net and functionality of both scenarios are exactly the same except a big area difference.
My questions then are:
How can I follow a block-wise (Hierarchical) design without adding area overhead (like unnecessary buffer insertion on I/O or non-clock nets)?
what criteria does synthesis tool use for inserting buffer on nets? how buffer insertion can be controlled in an efficient way to avoid adding unnecessary gates?
How can synthesis flow be controlled such that I follow a block-wise (Hierarchical) design (Scenario1) but from synthesis tool point of view it can be compiled like a non-hierarchical design (like Scenario2)? (I tried ungroup -all -flatten, but it just removes the hierarchy)