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I did get in troubles with my student project circuit below!

The purpose is to amplify difference between two inputs. Specifically, 20mV and 10mV are connected with input to get 1V at the last OpAmp's output.

The problem is when two input are grounded,the output offset voltage of OA1 and OA2 comes to saturation in reality. I attempted to find out what problem is but it doesn't make sense.

As I figured, I used a potentiometer to adjust the offset voltage because I thought the offset voltage is just 20-30 mV, but in fact, it wasn't.

What's the cause of this problem?

Here is my circuit on proteus.

schematic


enter image description here that is exactly what you asked me to do..right?


EDIT

Let me explain how I calculated the component values in the circuit. First, with \$U_1\$ we have that $$ \begin{split} V_- &=\frac{(V_1-V_{01})R_2}{R_1+R_2}+V_{01}\\ V_+ &=\frac{(V_{02}-V_{01})(R_3+R_4)}{R_3+R_4+R_5}+V_{01}\\ \\ \implies & \frac{(V_1-V_{01}) R_2}{R_1+R_2}=\frac{(V_{02}-V_{01}).(R_3+R_4)}{R_3+R_4+R_5}\quad (\text{because }V_+=V_-) \end{split} $$
$$ \implies V_{01}\left[\frac{R_2}{R_1+R_2} - \frac{R_3+R_4}{R_3+R_4+R_5}\right]=V_1\frac{R_2}{R_1+R_2}-V_{02}\frac{R_3+R_4}{R_3+R_4+R_5}\label{1}\tag{1} $$ As for U1, the same holds for U2: we have $$ \begin{split} V_- &=\frac{(V_2-V_{02})R_7}{R_7+R_6}+V_{01}\\ V_+ &=\frac{(V_{01}-V_{02})(R_4+R_5)}{R_3+R_4+R_5}+V_{02}\\ \end{split} $$
And again, since \$V_+\$ is also equal to \$V_-\$, $$ V_{02}\left[\frac{R_7}{R_7+R_6} - \frac{R_4+R_5}{R_3+R_4+R_5}\right]=V_2\frac{R_2}{R_1+R_2}-V_{01}\frac{R_4+R_5}{R_3+R_4+R_5}\label{2}\tag{2} $$ Assuming that \$R_3=R_5, R_1=R_6, R_2=R_7\$, from \eqref{1} and \eqref{2} we have $$ V_{02}-V_{01}=\frac{R_2(2R_3+R_4)}{R_4(R_2+2R_1)+2R_3R_1}(V_1-V_2)\label{g}\tag{G} $$ (I tested this equation on Proteus and it seems to be right) So now... how can I chose resistor’s value suitably to make this circuit work well?

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  • \$\begingroup\$ does this happen in reality or in simulation? If only in simulation, can you try an opamp that isn't as terrible as the LM741? \$\endgroup\$ – Marcus Müller May 22 at 6:51
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Edit: by using the circuit formulas for the input voltages \$V_+\$ and \$V_-\$ of the OpAmps \$U_1\$ and \$U_2\$ and taking into account that their differential gain \$A_d\$, however being very high, is finite i.e. we have $$ V_{01}=A_{d}(V_{+}-V_{-})\big|_1\quad\qquad\quad V_{02}=A_{d}(V_{+}-V_{-})\big|_2 \label{ad}\tag{AD} $$ I found that the circuit is unstable, no matter how the values of resistors \$R_3, R_4, R_5\$ are chosen and I show below how to prove it. Of course, the topology of the positive feedback loop could be modified in order to stabilize the circuit, but then you should answer to this very basic question: "Why do a positive/negative feedback mix is needed for this application?"

The problem with your circuit is that the resistors \$R_3,R_4, R_5\$ add a positive feedback loop to the couple of operational amplifiers \$U_1\$ and \$U_2\$: when the two inputs are grounded, the input stage of your amplifier looks as below

schematic

simulate this circuit – Schematic created using CircuitLab

This implies that every circuit asymmetry (not only the offset voltage, but perhaps also noises or leakage currents) make the outputs of the two amplifiers rising up to \$\pm V_{o_\mathrm{sat}}\$ (the sign of the output depends on the sign of the maximum circuit asymmetry your circuit experiences). And the problem cannot be solved simply by changing the values of the feedback resistors, as the analysis below shows.
The starting point are the expressions of the voltages at the input of the OpAmps: $$ U_1\:\left\{ \begin{split} V_- &=\frac{(V_1-V_{01})R_2}{R_1+R_2}+V_{01}\\ V_+ &=\frac{(V_{02}-V_{01})(R_3+R_4)}{R_3+R_4+R_5}+V_{01}\\ \end{split}\right. \\ U_2\: \left\{ \begin{split} V_- &=\frac{(V_2-V_{02})R_7}{R_7+R_6}+V_{02}\\ V_+ &=\frac{(V_{01}-V_{02})(R_4+R_5)}{R_3+R_4+R_5}+V_{02}\\ \end{split}\right. $$ Then, by using \eqref{ad} we get $$ \begin{split} V_{01} & = A_d (V_+ - V_-)\big|_1\\ & = \left[\frac{R_2}{R_1+R_2}(V_1 - V_{01}) - \frac{R_4+R_5}{R_3+R_4+R_5}(V_{02} - V_{01})\right] A_d\big|_1\\ \\ V_{02} & = A_d (V_+ - V_-)\big|_2\\ & = \left[\frac{R_7}{R_7+R_6}(V_1 - V_{01}) - \frac{R_4+R_5}{R_3+R_4+R_5}(V_{01} - V_{02})\right]A_d\big|_2. \end{split} $$ Now, assuming \$A_d\big|_1=A_d\big|_2\$ and \$R_1=R_7\$, \$R_2=R_6\$ by the above formulas we get $$ \begin{split} (V_{01} - V_{02}) &\left[1 + \left( \frac{R_2}{R_1+R_2} - 2 \frac{R_4+R_5}{R_3+R_4+R_5}\right)A_d \right]\\ & = \frac{A_d R_2}{R_1+R_2}(V_1 - V_2) \end{split}\label{dg}\tag{DG} $$ From equation \eqref{dg} we see that in order for the feedback to bee negative, i.e. for the term multiplying the output voltage \$(V_{01} - V_{02})\$ to be \$>1\$, the following condition needs to be fulfilled $$ \frac{R_2}{R_1+R_2} \gg 2 \frac{R_4+R_5}{R_3+R_4+R_5}\label{fbc}\tag{FBC} $$ However, for every physically admissible value of the resistances involved, condition \eqref{fbc} is always false: to see this, note that $$ \frac{R_2}{R_1+R_2}=\kappa <1 $$ and if we assume \$R_5 = R_3\$, \eqref{fbc} implies that $$ \begin{split} 2\frac{R_4+R_3}{2R_3+R_4} & \ll \kappa\\ 2 (R_4+R_3) & \ll \kappa (2R_3+R_4)\\ &\Updownarrow\\ 2(1-\kappa)R_3 &\ll (\kappa -2)R_4 <0 \end{split} $$ which is clearly false.

Possible solutions

  • Change the topology of your circuit in order to reproduce the standard instrumentation amplifier topology. This will assure you have a high gain and an adequate CMRR i.e. you can
  • Assuming that you really need a circuit with positive feedback as the one you designed, you have to change the structure of your feedback networks: for example you can connect two resistors between the reference ground and each positive input of \$U_1\$ and \$U_2\$. Then \eqref{fbc} is no more requried and, using the same method of analysis shown above you should find a new on and see if is physically realizable.

EDIT: In order to keep the overall gain as high as required, an easy way to proceed is to change the gain of the second stage: for example, putting \$R_8=R_{10}=1.5\mathrm{k}\Omega\$ guarantees that the second stage of the circuit, i.e the differential amplifier made of \$U_3\$ has a voltage gain \$A_v\$ of \$100\$, making the overall voltage gain strictly greater. Note however that nothing is for free in circuit design: rising the gain of a stage lowers its bandwidth since the \$GBW\$ is kept (customarily) constant by circuit design, thus you can amplify weaker but slower signals. After all, you are using the almighty LM741.

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    \$\begingroup\$ Comments are not for extended discussion; this conversation has been moved to chat. Any conclusions reached should be edited back into the question and/or any answer(s). \$\endgroup\$ – Dave Tweed May 23 at 21:10
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    \$\begingroup\$ Calculation does not help because it cannot reveal instabilties. For an opamp with positive feedback, even a simulation program will find a stable bias point (in case of DC or ac analyses). Only a TRAN analysis in the time domain will show that the circuit will saturate.. \$\endgroup\$ – LvW May 28 at 6:57
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    \$\begingroup\$ Yes - it is a mix of pos. and neg. feedback loops - but it is easy to show that the pos. feedback governs. Positive feedback is allowed only for loop gains below +1 (unity). \$\endgroup\$ – LvW May 28 at 13:23
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    \$\begingroup\$ I do not know how SunnyskyGuy did simulate - however, it seems he was using ideal opamp models. I did a SPICE-simulation with REAL models and a supply that was switched-on at t=0. This is the most secure method to reveal instabilities. \$\endgroup\$ – LvW Jun 1 at 8:28
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    \$\begingroup\$ I agree it has many meta conditions to be unstable . tinyurl.com/y5drwznj A real puzzle why a bad design would be shown to a student \$\endgroup\$ – Sunnyskyguy EE75 Jun 3 at 13:21
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Try this circuit for U1 & U2 (same U3 differential amplifier as in your circuit, but increase that 100 ohm load to at least a few K).

Looks like you've got positive feedback in your circuit that is causing the op-amps to rail.

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ thank you so much..But I was demanded to build a circuit like that..So I just want to adjust or add something in this circuit like resistor value or anything else,not to replace by another..So do you have any solution in my case? \$\endgroup\$ – STUDENT STRANGE May 22 at 17:19
  • \$\begingroup\$ I believe the circuit is unstable on a knife edge and will only work (only) in simulation. So maybe you have learned something about simulation vs. real life? Try simulating a very small AC input on top of the a DC input. \$\endgroup\$ – Spehro Pefhany May 22 at 18:09
  • \$\begingroup\$ thank you..I will try it \$\endgroup\$ – STUDENT STRANGE May 23 at 3:00
  • \$\begingroup\$ No need to try, same problem with input offset voltage on 741 \$\endgroup\$ – Sunnyskyguy EE75 May 30 at 17:34
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Your Op Amps have more input voltage offset than the DC input applied. So null adjust would be required.

Both circuits work but the non-inverting input has better COmmon Mode rejection even with this Ideal Op Amp and ideal resistors.

enter image description here

Here I applied the same 10 mVdc differentials but added 1Vp sine common mode.

here with AC common mode removed. enter image description here The output DC is almost correct and errors due to insufficient gain used in my model. (100k) just FYI.

Whenever signals out do not make sense examine all the voltages at every node and see why it makes sense. Then correct your offset with null pot on pins 1,4 to Vee.

Read up on INA IC's which use laser matched R's

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    \$\begingroup\$ SunnySkyguy......the first circuit is rather tricky and it is not easy to see if it works or not...are you sure it works? Even with REAL opamps? I have discovered that that neither DC nor AC analyses can reveal a possible instability. But a TRAN simulation with a supply voltage which is switched on at t=0 shows that the opamps go immediately into saturation. And this is not a surprise. For each opamp, the pos. feedback is dominating above the neg. feedback. \$\endgroup\$ – LvW May 31 at 9:03
  • \$\begingroup\$ Since the shared Rgain feedback is inverted by crossover to the other side, it is not positive feedback. the bigger problem is 4 R tolerance stack up instead of 2 and low input impedance \$\endgroup\$ – Sunnyskyguy EE75 May 31 at 14:54
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    \$\begingroup\$ So, if it is - in your view - not positive feedback, it must be negative feedback. Please, can you show me at which part of the circuit we have a sign inversion? \$\endgroup\$ – LvW May 31 at 15:21
  • \$\begingroup\$ Looking at the overall gain of 1st stage as a product of -ve transimpedance and differential output voltage ratio of 2/3 due to the crossover yet relative to the Vce, crossing the Vce level, changes the polarity of the voltage feedback such that the gain would increase from -2 to +4 as diff. Gain of 1st stage and x50 of 2nd stage but overall still negative feedback due the opposing polarity of input current in each of the 1st two stages. FWIW @LvW \$\endgroup\$ – Sunnyskyguy EE75 Jun 2 at 16:50
  • \$\begingroup\$ I must admit that I cannot follow. (1) "product of -ve transimpedance and diff. output voltage" ? (2) What is Vce ? (3) role of "input current" ? Does this mean that the circuit needs a diff. input voltage to be stable? I repeat: TRAN simulation with REAL opamps and a ramping supply voltage reveals saturation. \$\endgroup\$ – LvW Jun 3 at 5:26

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