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For the purpose of testing a MCU and it's interrupt handling I want to design a circuit to generate interrupts. Ideally I would use a relaxation oscillator, but my supply is constrained to 0V and +3.3V and the output signal should also be close to 0V / 3.3C.

What would be a good possibility to overcome the problem of not having (and not wanting to have) a negative voltage supply?

relaxation oscillator

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You can use a CMOS-input rail-to-rail in/out op-amp (pick one suitable for 3.3V operation) and add another resistor from the non-inverting input to the positive supply to bias the op-amp. For example, all resistors 10K and select the capacitor to yield your desired frequency. Hopefully you have a Schmidt trigger input on the MCU interrupt input, because the rise and fall times may not be very fast, depending on the op-amp.

That resistor is required because without that it either will not oscillate (hang with the output low) or will give a very low duty cycle, depending on the output saturation voltage and the offset voltage at the inputs.

Note that you are using an op-amp as a comparator here, so some op-amps will be even more unsatisfactory than others.

Or just use a CMOS 555 such as TLC555.

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This circuit will still oscillate if it's moved to a single supply rail. You may have to turn up the gain on the bottom two resistors in the positive feedback pathway. Make sure you select an op amp that is rail to rail or has a high common mode range.

Interrupts need to be very clean, it would be wise to take the output of this circuit and clean it up with a Schmidt trigger to make sure the rising and falling time is very fast and noise is reduced. The transition time of voltages between Voh and Vol must be kept to a minimum. On some processors metastablity can result.

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I'd suggest that you would use another MCU to generate interrupts.

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