# Increasing drain current, decreases common-mode level

The basic idea behind the CMFB setup is that increased output common-mode level feeds back into the gate-source of the triode devices and causes drain current to increase and hence output CM level to drop again -> I'm confused there - how does increased drain current cause output CM level to decrease.

My understanding was as follows, if drain current increases then if I roughly assume M9, M10 to have some Vds channel drop, then output CM level would roughly be Vdd - R_eq1(Id) and so increasing Id decreases CM level. But, the other argument is that the output CM level is just the voltage drop of M5, M6/M7,M8 and again approximating as a resistor, that would mean output CM level is R_eq2(Id), so increasing drain current, increases output CM level?

Can someone explain in detail how increasing drain current causes output CM lvl to drop

That's simple:

1. Say Vout1 has increased by a little bit

2. The current in the left branch then increases as the result of the CM feedback loop

3. The Vsg of M9 is fixed

4. The drain current of M9 wants to increase

5. Due to channel-length modulation the Vsd,9 must increase, why?

6. By the same token, the Vsd of the transistor below M9 must increase

7. So Vout1 must decrease to allow for the change in the current

8. Decreasing Vout1 causes the drain current to decrease as well

9. A decreasing drain current works in reverse to what said above

10. It eventually rises Vout1 up to the value it was before the change was made

11. The CMFB used here doesn't constrain a certain value on CM voltage level though

12. The same holds for Vout2

That's how CMFB works..

Note that the kind of analysis we're doing here is large signal, so in large signal analysis Req1 and Req2 are not fixed resistors, so your KVL equations fail to interpret the correct change in CM voltage level because you're not considering the change in Req1 and Req2 as well. You don't even know in which way they change. So you can't predict what happens to CM voltage level based on unknown values of Req1 and Req2.

View those PMOS (4 of them), at the top, as resistors.

When the 2 Vout nodes rise (because Vcm rises), the resistance from node P to ground will reduce,

With fixed VB, more current flows thru M5 and M6, pulling more current from the two Vout nodes, which drops the Vcm.