5
\$\begingroup\$

I'm making a prototype based on the W7500P reference design, the latest version (updated 6 months ago) specifies the need for a Power over Reset IC.

I do not understand the point of this component over more traditional resets, and I'm questioning wether or not it is necessary to include this. The WizWiki W7500P developement board (made by the same company) does not include this component.

Here is the reference design :enter image description here

\$\endgroup\$
  • \$\begingroup\$ How do you define "traditional reset", just an RC, or an RC with a schmitt trigger? How well behaved is your power-on ramp? A POR IC will handle slow ramps better and will handle brownouts. \$\endgroup\$ – Mattman944 May 23 at 16:26
11
\$\begingroup\$

Power-on detectors (also: brownout detectors) check whether the supply voltage has been stable within a certain range over a certain amount of time and let go of the reset line only when that happened.

The problem with unstable power is complex ICs fail partly, so while e.g. an internal EEPROM holding calibration data may only return garbage, the CPU already or still runs with that, now garbage, data.

Whether you need something like this depends on how reliable your device needs to be. If it's interactive so the user can check for unintended behaviour, you probably don't need it. If the device is expected to run unattended, you certainly need such a detector.

Some µCs have this function already built-in.

\$\endgroup\$
  • 2
    \$\begingroup\$ +1 For giving you 9000 rep and a good answer with some suggestions for application :) \$\endgroup\$ – KingDuken May 23 at 16:42
2
\$\begingroup\$

A POR chip usually contains a voltage reference, precision comparator, threshold-setting resistors, and an output pulse former (monostable). It is designed to operate on very low voltages, even though the trip point might be up around 3 v or 5 V. The one on your schematic includes an input for a manual reset switch.

The idea here is that as the system power rail ramps up from 0 V to 3.3 V or whatever, the POR chip wakes up first and holds the uC reset input in the reset state until after the power rail is up to full voltage and has stabilized. Also, if the system power dips below the threshold value it forces a reset.

It is up to you to decide if you need all of these features or protection.

\$\endgroup\$
2
\$\begingroup\$

The W7500P reference design is a standalone implementation. As such it is unknown what will be driving the board (MCU choice). In this case it is prudent to provide a good level detector for Power On Reset to ensure the reset state of the device when power is applied or during power failure/return.

The WiZWiki-7600P development board has a MANUAL reset switch (Sheet2-D1) which assumes human presence to reset the device should it fail to initialize.

enter image description here

While perhaps acceptable for a development board this is not adequate for a finished product expected to reset gracefully and predictably for power on or power failure.

If you have an MCU with POR detection built in, or added to it, you can use this to reset your WizNet 7500, but you should ensure predictable reset conditions for you product.

There are a plethora of PMIC power supervisors to chose from, do yourself a favor and put one on your board. Many of these POR supervisors are SOT23 packages, so at the very minimum you should layout one on your board even if it's a DNP placeholder.
Be careful during part selection that some are active pullup and some are open Collector/Drain outputs.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.