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I have a question about a tutorial video from PSIM: https://www.youtube.com/watch?v=iATO3mUKBPc

In this video, a MOSFET circuit is created using LTSpice .lib files from Cree. The parasitic drain and source inductance is indicated in the video with a parallel resistor. This resistance value and also the parasitic inductance can be taken from the .lib file. For the MOSFET used in the video the following is given in the .lib file: Ls = 9n, R_Ls = 10, Rg = 11.4, Lg = 15n, R_Lg = 10, Ld = 6n, R_Ld = 10.

My question is why this resistance value of 10 ohms corresponds to a parallel resistance of the inductance. I always thought that the parasitic inductance and the resistance are present due to the pins of the package (like TO-247). However, to my knowledge, such pins would present a series connection of parasitic inductance and parasitic resistance. Can someone please explain to me why a parallel connection is assumed?

Thank you in advance!

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    \$\begingroup\$ More than likely the lead resistance is put in parallel with the lead inductance to keep SPICE happy. Force opening an inductor is a bad idea in the real world and in the simulation world it causes other problems \$\endgroup\$
    – user16222
    May 23, 2019 at 20:54

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After looking at the file, the parasitic inductance Lg and R_Lg have something to to do with gate timing. I can't post the circuit that I reverse engineered from the spice file because it would almost certainly violate the terms and agreements of downloading the file.

I can say this, in my opinion :

  • It doesn't look like this value of gate inductance is related to a physical construction of the gate. The inductance value is too high.
  • The model is unlike any mosfet model I have seen.
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  • \$\begingroup\$ I think the values for the inductances are acceptable. I have also found out from other sources that these 5-10 nH are realistic for these packages. But of course, I can be wrong. It is a pity that there is no documentation for the model. I am curious how close this model comes to reality. \$\endgroup\$
    – Noah
    May 24, 2019 at 10:01
  • \$\begingroup\$ Oh, another thing. Many mosfet models only replicate fet functionality, not how they are physically constructed, because manufacturers don't want their products to be reverse engineered from the spice file. Mosfet models usually replicate the measured values seen in the datasheet and may have some 'fudge factors' in them to make them match the functionality of the device. That may be what is going on here. \$\endgroup\$
    – Voltage Spike
    Aug 1, 2019 at 20:37

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