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We are testing a fabricated chip with expected output current of around 4mA which is then used to charge a button cell. The input is from a PV cell. However, when we attach an oscilloscope probe onto one of the pin outs of the chip (i.e. the ring oscillator and the clock), we detect a significant current drop at the output, from 4mA to around 1mA. The current from the PV cell also drops.

what would be the cause of this current drop?

We tried with a different oscilloscope, and still detected a drop in current, albeit of a different value.

Attached is the block diagram of the DUT.

implemented in 65nm CMOS

note: the buffer is connected to the rectifier through offchip capacitors.

enter image description here

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  • \$\begingroup\$ Measuring current is fairly difficult, because the act of measuring it changes the result. \$\endgroup\$ – hekete May 24 at 7:30
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    \$\begingroup\$ I am having to guess what this circuit is doing, maybe a charge pump? The ring oscillator is sensitive to the capacitance of the scope probe. Attaching the probe lowers the frequency and changes the circuit behavior. You shouldn't have brought the oscillator output directly out to a pin, you should put a buffer before the test point, assuming that the left blue hexagon is just a test point. \$\endgroup\$ – Mattman944 May 24 at 7:49
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    \$\begingroup\$ Most likely there is a problem with your Ring oscillator design. I would use a Schmitt Trigger with RC instead. But too late. Show the Ring Osc design \$\endgroup\$ – Sunnyskyguy EE75 May 24 at 8:06
  • \$\begingroup\$ You must use a 10:1 scope probe which is typ. 9 pf //10M which should never bother a good clock design. But in your case it may slow down the clock from load capacitance. Some Ring Osc uses string of inverters in a loop each with <1pF so putting a 9pF probe on the output adds latency from current limit. dV/dt=Ic/C \$\endgroup\$ – Sunnyskyguy EE75 May 24 at 8:09
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You must use a 10:1 scope probe which is typ. 9 pf //10M which should never bother a good clock design. But in your case it may slow down the clock from load capacitance. Some Ring Osc uses string of inverters in a loop each with <1pF so putting a 9pF probe on the output adds latency from current limit. dV/dt=Ic/C

schematic

simulate this circuit – Schematic created using CircuitLab

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