I need confirmation that the following circuit diagrams are correct for their Boolean expressions. I've been told that each logic circuit must have a MAXIMUM of 4 NAND gates, however, I cannot manage any less than 5. Thanks in advance.
Let me put across how I'd go about the first one and leave the second one to you. Since there is an already simplified expression in your case i.e (no further simplification possible using laws of boolean algebra), the only way around in such cases to look at optimization of gates using an alternative implementation, which can be done by taking a double negation (since NAND is required) over the entire expression and solving it using De Morgan's law. In this case that would be to reuse the input A to reduce a few gates.
I made the circuit using circuit verse which you can check out here. You can also simulate with any permutation of inputs there.Please let me know if this answers your question.
Hint for the second one: It must be safe to assume that negated C is already available as a direct input by estimating the least number of gates using the above method.