# Linear Regulation Concept Confusion

I was watching one of Jacob Baker's videos (http://cmosedu.com/videos/f10/ece5472/lec1_ece5472_video/lec1_ece5472_video.html)

At minute 19:30, he explains the concept behind linear regulation:

His Explanation

He explains it by saying that if the output regulated node is at 1.9V and reference is 1.8V, then the gate of the PMOS device will increase, decreasing current in the branch and a smaller voltage drop across the load resistor hence the output regulated voltage goes down to 1.8V.

My Explanation

The way I see it is that if the gate of the PMOS device goes up and if I follow this graph:

Then we would switch to a Vgs curve which has a less steep slope and thus the PMOS device would actually have a higher resistance, dropping a larger voltage and thus bringing output node down to 1.8V.

Is my understanding valid? (I hate thinking of PMOS devices as fixed resistors(like a lot of authors simplify it to be) since it doesn't satisfy KVL).

• Increase in the gate voltage decreases the Vgs voltage in a PMOS hence reducing the PMOS current and the load current. And you can treat the voltage regulator as a noninverting amplifier with the input voltage equal to Vref.
– G36
May 26, 2019 at 4:10
• Why do you say "it doesn't satisfy KVL"? If you aren't operating this circuit somewhere there's changing magnetic flux through the circuit loops, it certainly will satisfy KVL. May 26, 2019 at 4:15
• @ThePhoton - he said considering a FET as a fixed resistor violates KVL. I imagine considering a FET as a fied resistor violates most things :-). May 26, 2019 at 8:55

His explanation is "correct enough" but less clear than it could be.

Your explanation is also "correct enough", but the use of the transfer function curves add more complexity than is needed for a basic explanation.

A basic statement, which is reflected in the transfer function curves is
"A PMOS transistor will exhibit decreasing drain-source resistance as the gate is driven more negative relative to the source".
The opposite also applies - making the gate less negative relative to the source increases Rds.

With the above basic concept to work with, the regulator operates by

• increasing Rds if Vout is too high,

• and reducing Rds if Vout is too low.

• Rds and Rload form a voltage divider that cause the above action to drive Vout in the correct direction.

In the circuit in question the opamp / comparator is arranged so that if Vout is > Vref then Vgate is driven higher so |Vgs| decreases so Rds increases so Vout decreases.

Is that easier to understand?
[Explanations that seem simple to one person may not appear simple to another].

• Perfect. That's what I had in mind anyways. Personally, I love using MOSFET I/V curves to explain stuff and I always have them in mind so I've gotten used to using them for explanations. May 26, 2019 at 17:51
• @AlfroJang80 Yes - the curves properly explain what is happening , but using them risks hiding the simplicity of the basic explanation. May 26, 2019 at 20:50
• Yeah, I definitely agree there. Now that I think of it, I suppose you could also explain it by saying (in the case of the NMOS devices), a higher gate source voltage increases the number of the free electrons available for conduction in the channel and thus resistance decreases (NMOS device). Lot's of ways to explain one concept. May 27, 2019 at 3:30