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In configuring the sampling time for the internal ADC of a micro-controller (STM32F446RE) to sample the output of a current sensor connected to a PWM controlled motor, the sampling is triggered at 100kHz and I have a window of between 3 and 225 ADC clock cycles (22.5MHz) over which to hold the sampler open - my assumption is that the longer its open the less noise I'm going to see in the results. Is this correct, or is there a point where other factors come into play that would make a more intermediate sampling duration preferable?

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That understanding is correct. If your ADC clocks are fast enough so that you can do 225 cycles of acquisition for one sample, then by all means do that.

Things that might go astray, as in basically every ADC, is that you might be loading the voltage source you're observing with your ADC. Of course, charging the ADC sample&hold capacitor for longer might increase the overall loading, but it might also allow the voltage source to catch up. The amount of current into the ADC or the capacity of the sample and hold can typically be read from the datasheet. If in doubt, add a voltage follower.

schematic

simulate this circuit – Schematic created using CircuitLab

Adding a voltage follower is also an excellent opportunity to also add an RC low pass filter, if your signal including noise isn't inherently band-limited to below Nyquist frequency anyway. Your noise has (near) infinite bandwidth, but your ADC is only meant to observe \$f_\text{Ny}=\frac{f_\text{sample}}2=50\,\text{kHz}\$ of bandwidth! So, filtering out anything above 50 kHz will lead to less noise being aliased into the 50 kHz it observes:

schematic

simulate this circuit

The ADC will of course load the voltage divider that RC low pass filter is, but at the low impedance of R1 and the sufficient drive strength of about any opamp, this should be negligible. Upon closer consideration, you'll notice that C1 now smooths out the noise to begin with, so you can then reduce the sampling time (if there's any other reason to do so, for example, need for higher sampling rate because of clocking reasons in the MCU).

Of course, if you know better than I do what frequency ranges you're looking for, you might design a better RC low pass, or even an advanced active filter with online tools (or pen and paper). The 50 kHz cutoff filter I sketched above is probably not a good choice – but it's hard to know a good choice when you don't know at which frequencies to expect signal components! In a PWM system, however, you expect harmonics at every odd multiple of the PWM frequency, whereas you probably mostly care about the current that flows on average over a few PWM cycles through your motor – model how fast the current through your motor is supposed to change, and filter so that this is preserved, but not much higher frequencies.

In general, if your CPU doesn't break a sweat dealing with 100 kS/s, then maybe go for the 50 kHz analog filter (or your signal being bandlimited below that from the start), and do the filtering and decimation in software: a simple FIR filter¹ running on your ARM can have a much steeper frequency response than a reasonably complex analog filter. That's what us radio folks do: analogously filter as much as necessary for the ADC and computation system to deal with the signal, then do the fine-filtering in digital domain, where math is exact (unlike real-world capacitors) and easy, and can be linear-phase.


¹ please don't build a Butterworth "just because it was the first filter I found" – it's not a filter type typical for digital filters, and it's rarely actually what people want, it's just nice because it's flat in passband and easy to build in analog, not in digital)

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There is no downside to having longest possible sampling period unless it starts to limit the sampling rate. It also does not result in less noise if the sampling capacitor already gets fully charged in shorter time.

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Many ADC have about 5pF Csample, and 1Kohm Rseries (plus the sampling FET channel resistance). This is a 5,000 picosecond TAU.

The Neper tells you the improvement of accuracy, given each additional Tau of settling.

Neper = 8.6 dB per Tau, or about 1.6 bits.

For a 16 bit ADC, you need 10 nepers or 10 Tau settling, or 5*10 = 50 nanoseconds.

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is there a point where other factors come into play that would make a more intermediate sampling duration preferable?

One such reason could be oversampling the signal, which means taking multiple ADC samples and then combining them in software. Depending on the method used for combining/downsampling, this can reduce noise or increase resolution, or both.

For example, taking 4 samples instead of 1 and then just summing them together usually halves the noise level and thus increases resolution by one bit. But a simple summing filter works well only if the noise is white noise, and might actually increase the noise level if there is a high-frequency noise signal present.

In any case, having more samples available to software gives more signal processing freedom, while requiring more CPU power and shorter sampling time.

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