The architecture displayed here doesn't have any sort of cache -- it's too simple for that. You can think of "Data memory" as RAM, but notice that this is a "Harvard architecture" machine, which means that it has separate data and instruction memory. This can simplify things for educational purposes, but is a very rare design for modern general-purpose CPUs (although it is still popular for microcontrollers.)
Regarding your brief mention of instruction formats, a note: every CPU family/architecture has its own instruction format. So we reading your question have no way to know what you're talking about when you say "i format", because whatever it is, it's probably specific to whatever book or other source you are reading this diagram from. (Although from googling it and finding some materials you might be working from, I suspect it is the "immediate" format, in which a number is embedded directly (i.e. "immediately") into the instruction.)
The function of sign extension, in general, is to take a signed number and "widen" it to more bits. (If you're not already familiar with two's complement number representation, now is the time to read up on it.) Widening an unsigned number from, say, 8 to 16 bits is easy: just put 8 zeroes on the front. Widening a two's complement signed number is slightly harder, because the top bit is the sign bit. But it's not much harder: you just copy the sign bit to the left. For a positive number, you pad the front with zeroes; for a negative number you pad it with ones. (You should try to understand why this is true.)
So all the "sign extend" block is doing here is taking the 16-bit immediate number from the instruction, and widening it to some wider number of bits (probably 32, although it's not directly indicated in the diagram) for use by other parts of the processor which need a wider number. In this case, it looks like the number is then used as either a jump offset (multiplied by 4) if PCSrc is true, or as an arithmetic operation input if ALUSrc is true.