I'm looking for advice in making sure the FET driver I've chosen is capable of driving the FETs I've chosen with turn on time as low as possible.

I'm going to use the LMG1210 and EPC2020 with 12V rails switching at \$500kHz\$. The datasheet says the gate charge (\$Q_g\$) is \$16nC\$ typ. The peak current of the LMG1210 is \$3A\$. Am I correct in saying the minimum turn on time of this FET can be calculated using:

\$T_{on} = \frac{Q_g}{I_g} = \frac{16nC}{3} = 5.3nS\$


Realize the dI/dt, perhaps 3 A in 3 ns, across 3 nH total inductance (if you are lucky), will cause 3 volts upset to the predictions.

What are the package inductances for the GAN fet and for the driver IC? Without understanding those numbers, it’s just guessing.

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  • \$\begingroup\$ Identifying loop and package inductances is key for GaN FETs. TI state: "The gate loop and common source inductance are also minimized in the GaN FET power stage package to be below 200 pH. High parasitic inductance in these loops can cause a significant power loss" See ti.com/lit/wp/slyy071/slyy071.pdf page 4. \$\endgroup\$ – Peter Smith May 26 '19 at 13:10

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