I'm trying to write verilog to synthesize a circuit which operates as follows:
- At the rising edge of SET if RESET is low then OUT is set high and it will be reset when RESET is high (the first cycle in the image)
- At the rising edge of SET if RESET is low then OUT is set high. However, when RESET is high where SET is also high, OUT is not reset at that time but rather reset at the falling edge of SET signal(the second cycle in the image)
- At the rising edge of SET if RESET is high then OUT is low (the third cycle in the image)
This would be simple if reset goes high when SET is low. However, because SET and RESET can be high at the same time and this makes it difficult. I don't know how to proceed.
So how to write a verilog code to do this? What would be a good approach to do this?