I'm trying to write verilog to synthesize a circuit which operates as follows:

  • At the rising edge of SET if RESET is low then OUT is set high and it will be reset when RESET is high (the first cycle in the image)
  • At the rising edge of SET if RESET is low then OUT is set high. However, when RESET is high where SET is also high, OUT is not reset at that time but rather reset at the falling edge of SET signal(the second cycle in the image)
  • At the rising edge of SET if RESET is high then OUT is low (the third cycle in the image)

This would be simple if reset goes high when SET is low. However, because SET and RESET can be high at the same time and this makes it difficult. I don't know how to proceed.

So how to write a verilog code to do this? What would be a good approach to do this?

enter image description here

  • \$\begingroup\$ Do you just want to know how to express this in Verilog, or do you also want to be able to synthesize this and program an FPGA (for example) with this logic? \$\endgroup\$ – The Photon May 27 at 17:27
  • \$\begingroup\$ Actually I want to do design real circuit with FFs and logic gates so after synthesize and get RTL circuit, I will design the circuit myself. \$\endgroup\$ – anhnha May 27 at 17:31
  • \$\begingroup\$ Do you have another clock signal available in your system, and is it okay for this logic to delay up to 1 clock cycle before responding to rising edges of SET and RESET? \$\endgroup\$ – The Photon May 27 at 17:32
  • \$\begingroup\$ No, there's no other clock signal. Only SET and RESET as inputs. Without clk so it's a no for the second question. \$\endgroup\$ – anhnha May 27 at 17:36
  • \$\begingroup\$ So basically SET and RESET are the "clock signals" then. Are there any time constrains which apply for them? E.g. can you guarantee that there is at least a delay of "x" between a SET and a RESET pulse and that a pulse last for at least "y"? \$\endgroup\$ – Christian B. May 28 at 7:25

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