# Cascode Amplifier Biasing Sequence

I'm trying to understand the proper biasing procedure of a cascode distributed amplifier part that requires three power supplies. A positive drain-source VDD, a negative gate-source VGG1, and a second, positive gate-source VGG2.

The recommended biasing procedure is for the bottom MESFET VGG1 to be supplied, then the drain-source VDD, and finally the top MESFET VGG2.

I don't know much about amplifier operation, I was tasked to document the proper biasing procedure for parts and determine if there will be an issue. Case in point the VGG2 may be supplied by a linear regulator that's always on while VGG1 and VDD will be controllable. I want to understand what the ramifications of having VGG2 always being on

***EXTRA: I could also use help in trying to model the situation in ADS to have a visual representation of the problem.

In order for the MESFET $$\\mathrm{FET_1}\$$ to work in saturation region, you should require that $$|V_{DS_\mathrm{FET_1}}|\ge |V_{P_\mathrm{\,FET_1}}|+|V_{GS_\mathrm{FET_1}}|, \label{1}\tag{1}$$ where $$\V_{P_\mathrm{\,FET_1}}\$$ is the pinch off (threshold) gate-source voltage of the MESFET. This implies that the quiescent value of $$\V_{GG_2}\$$ must be chosen in such a way that \eqref{1} is satisfied, and in turn this implies that $$V_{GG_2}\gg V_\gamma,$$ where $$\V_\gamma\$$ is the threshold voltage of the $$\\mathrm{FET_2}\$$ Gate-Source GaAs Schottky junction: normally, this is not a problem since when $$\V_{DS_\mathrm{FET_1}}\$$ is at its quiescent value $$\V_{DSQ_\mathrm{FET_1}}\$$, then $$V_{GSQ_\mathrm{FET_2}}=V_{GG_2}-V_{DSQ_\mathrm{FET_1}}<0$$ However, if you apply $$\V_{GG_2}\$$ before applying $$\V_{GG_1}\$$ then, since $$\V_{DS_\mathrm{FET_1}}\$$ is still nearly zero, the $$\\mathrm{FET_2}\$$ Gate-Source GaAs Schottky junction would became forward biased with a high value of gate current $$\I_{G_\mathrm{FET_2}}\$$ which would permanently damage the device: in sum in order to avoid permanent damages to the MESFETs, it is better to follow the recommended biasing sequence.
• Since $V_{GSQ_\mathrm{FET_1}}$ is usually <0 for MESFETs, it is possible to use a positive $V_{SS_1}$ instead of a negative $V_{GG_1}$: to my knowledge, DC biasing between RF/MW stages, need not to be isolated. However, years ago $V_{SS}$ biasing was not advocated because it was difficult to realize a source decoupling network with adequate low impedance at high frequency: this was especially true for low noise stages. – Daniele Tampieri May 29 at 5:53