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I am trying to migrate portions of a ZYNQ design from one platform to another. Part of the project is based on Avnet's ALI3 touchscreen kit. From the docs:

The 7-inch Zed Touch Display Kit includes a WVGA (800x480) LCD panel. To better understand the memory storage and bandwidth involved with this video resolution, let’s perform some calculations:

Video Resolution:

  • Active area = 800 x 480
  • Frame rate = 60 Hz
  • Pixel rate = 33.333333 MHz
  • Pixel format = 24 bits RGB

Video Storage Requirements:

  • (800 x 480) pixels x 24 bits/pixel = 9.2 Mbits

Video Bandwidth Requirements:

  • (800 x 480) pixels x 24 bits/pixel x 60 frames/sec = 533 Mbits/sec

The LCD panel has a serial LVDS interface. This means that the 24 bit parallel video interface must be serialized by a factor of 7:1, before being transmitted on four LVDS differential pairs. A fifth LVDS differential pair is used to transmit the clock.

Notwithstanding the significant rounding down of the Video Bandwidth Requirements result, it is not obvious to me why the video "must" be serialized by the specific factor of 7:1.

Is this an industry standard video thing, or does 7:1 follow from the numbers given? What am I missing?

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It appears to be an industry standard thing, yes: see this PDF.

For each clock period at the pixel clock rate, you have to transmit seven bits on each LVDS channel. Keen observers will spot that 4*7 is actually 28 rather than 24; the other four bits seem to be used for sync.

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  • \$\begingroup\$ Thanks for the linked white paper. It was exactly what I was looking for. In the Xilinx and Avent docs I've read, it's implied but never explicitly stated that the extra bits are used for something. \$\endgroup\$
    – Bort
    May 28 '19 at 15:13

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