This question might sound obvious for some, however, I found that I need to understand some VLSI fundamentals.

In Functional simulation setup and hold time are equal to zero, so we can simulate the design and have a data transition at an exact rising edge. My question is, once we simulate the RTL and validate its functionality, how to be sure that the synthesized design respects the setup time, in the context of FPGA and ASIC? Does the compiler add some delays automatically according to the gates library, so a data transition will happen after a clock edge? Do we need to set setup time with some constraints especially when dealing with ASIC?

  • \$\begingroup\$ A large exponent value of all states or a limit on latency may cause simulation out-of-memory errors, so constraints for time limits or critical dependencies help simplify the abstraction simulation if you run into trouble. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 May 28 '19 at 15:57

The synthesized design will include the actual delays associated with the gates and the interconnect. You can then use either simulation or static timing analysis to determine whether the design meets its timing constraints.

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