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Background

Currently I am working on a breakout board which allows me to connect a number of external boards (analog and mixed signal) to an Arduino Micro, using a variety of connectors. The breakout board is limited to two layers, and has to deal with nine analog sensor signals, as well as seven digital (SPI) signals, viz. clock (SCK), MISO, MOSI, and four chip-select signals (CS). The Arduino is configured for a 2 MHz SPI clock frequency, but I could not find any information about typical rise times.

The problem is that I am not sure what is the best approach to routing the digital signals on my breakout board. Since my question is pretty basic, I boiled it down to the minimal example described below.

Simplified problem

In this simplified example, I have a ground plane, an SPI clock signal (SCK), a chip select signal (CS), and a relatively large "keepout area," as illustrated in the figure below. Please note the example is not to scale: the actual trace length would be over 10 cm.

simplified problem

The pin assignment on the connectors cannot be modified, nor can I move/rotate the connectors or keepout area.

The basic problem is that the CS signal needs to cross over to the other side of SCK (2 MHz).

Assuming it is best to keep the SCK trace on one plane, intact, there are several options for CS, as illustrated in the figure below:

  1. use vias to route CS under SCK (orthogonal, with minimal gap in ground plane)
  2. use a jumper, or zero-ohm resistor, to jump CS over SCK (keeps ground plane intact, but adds extra components)
  3. use a detour around the keepout area (keeps ground plane intact, without extra components, but increases length of the trace considerably)

EDIT: Unfortunately, routing the entire CS signal around the SCK signal on the bottom plane is not an option. The actual board size would be around 10x10cm. Trace lengths will be around 10 cm, with an increase to 15 cm using option 3.

three options

Question

What would be the best choice, assuming the traces will be around 10 cm (with an increase to 15 cm for option 3), in terms of both signal integrity and electromagnetic emissions (EMI)?

I suppose I won't need to be overly concerned with high-speed design topics such as impedance matching and signal termination?

On the actual board, I have two CS signals which both need to cross SCK, MISO, and MOSI. Would that change things?

What I think

Given that the SPI clock frequency is 2 MHz, and based on what I've read so far, e.g. here and here, I suspect it might not make such a big difference, in my particular case. However, I don't have any experience to speak of, and I am unsure about the high frequency content of the clock edges.

I am inclined to keep the ground plane intact as much as possible, so that would imply the use of either option 2 or 3. Using option 3 on the actual board, I can route nearly all signals on the top plane, without actually crossing or breaking the ground plane, but the detours add some 5 cm to the trace lengths. Moreover, the result hurts the eye...

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  • \$\begingroup\$ Similar question, but different: electronics.stackexchange.com/q/233921 \$\endgroup\$ – djvg May 29 '19 at 14:39
  • \$\begingroup\$ Why don't you just keep each signal on a layer of its own? No need for vias. \$\endgroup\$ – Lundin May 29 '19 at 14:45
  • \$\begingroup\$ @Lundin: It's a two layer board. \$\endgroup\$ – djvg May 29 '19 at 14:46
  • \$\begingroup\$ Yes, and so you have 2 layers. \$\endgroup\$ – Lundin May 29 '19 at 14:46
  • \$\begingroup\$ @Lundin: that would create a very large gap in the ground plane, under the clock, which I believe is not a good idea. (you're right, in the example one could route along the edges on the bottom plane, but that is not an option for me) \$\endgroup\$ – djvg May 29 '19 at 14:49
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Maybe you can reduce the pad ( CS/SCK) and route between SCK and GND to connect CS. But I think using second layer is better , just add via to have a strong GND plane.

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