Verilog if else if construct

Question

I have verilog code that looks like this

begin
  if (condition)
       if(condition2)
       else if(condition3)
       else if(condition4)
  else
   ..logic..
end

This code compiles and simulates. My question is how would the simulator interpret the last else branch? Would it consider the else as a part of the nested if-else-if construct or the outer if construct.

Also, would synthesis result in an inferred latch for which of those constructs?

Programming languages generally do no mandate the use of else branch even for a if..else if construct.

But I want to know how Verilog being a HDL handles this? I could not find any specific mention in the LRM.

Answer 1

You have to look at the BNF to understand how code is parsed. Indenting makes code easier to read, but is meaningless for the compiler

conditional_statement ::= // from A.6.6
          [ unique_priority ] if ( cond_predicate ) statement_or_null
          { else if ( cond_predicate ) statement_or_null }
          [ else statement_or_null ]

And a begin/end is considered a statement, as well as another nested conditional_statement. So your code is illegal because there is no statement_or_null after if(condition4) Adding a null ; would make the last else go with the last if.

Once you have a completely legal always block, a synthesis tool looks at the flow of variable references across all possible branches. If there's a possibility that a variable could be read without first being written, then is gets implemented as a latch. It's a bit more complicated than that; do read your synthesis tool manual.