I have verilog code that looks like this
begin
if (condition)
if(condition2)
else if(condition3)
else if(condition4)
else
..logic..
end
This code compiles and simulates. My question is how would the simulator interpret the last else branch? Would it consider the else as a part of the nested if-else-if construct or the outer if construct.
Also, would synthesis result in an inferred latch for which of those constructs?
Programming languages generally do no mandate the use of else branch even for a if..else if construct.
But I want to know how Verilog being a HDL handles this? I could not find any specific mention in the LRM.
begin
andend
in to make the code unambiguous, then you don't have to worry (or remember the next time you read your code) what the standard says. (But my guess is, it goes with the innerif
) \$\endgroup\$else if
goes with the inner or outerif
? And if you know it goes with the innerif
, why do you think the rule forelse if
might be different from the rule forelse
? \$\endgroup\$else
also always have an immediately precedingif
? \$\endgroup\$else if
is also following anelse if
rather than a bareif
. Do you know whether it goes with the inner or outerif
? I still am not seeing whyelse
andelse if
could be considered different. \$\endgroup\$