I have verilog code that looks like this
begin if (condition) if(condition2) else if(condition3) else if(condition4) else ..logic.. end
This code compiles and simulates. My question is how would the simulator interpret the last else branch? Would it consider the else as a part of the nested if-else-if construct or the outer if construct.
Also, would synthesis result in an inferred latch for which of those constructs?
Programming languages generally do no mandate the use of else branch even for a if..else if construct.
But I want to know how Verilog being a HDL handles this? I could not find any specific mention in the LRM.