Verilog if else if construct

Question

I have verilog code that looks like this

begin
  if (condition)
       if(condition2)
       else if(condition3)
       else if(condition4)
  else
   ..logic..
end

This code compiles and simulates. My question is how would the simulator interpret the last else branch? Would it consider the else as a part of the nested if-else-if construct or the outer if construct.

Also, would synthesis result in an inferred latch for which of those constructs?

Programming languages generally do no mandate the use of else branch even for a if..else if construct.

But I want to know how Verilog being a HDL handles this? I could not find any specific mention in the LRM.

Just put begin and end in to make the code unambiguous, then you don't have to worry (or remember the next time you read your code) what the standard says. (But my guess is, it goes with the inner if) — The Photon, May 29 '19 at 16:57
How do you even know whether the first else if goes with the inner or outer if? And if you know it goes with the inner if, why do you think the rule for else if might be different from the rule for else? — The Photon, May 29 '19 at 16:58
@Photon I agree there are ways to avoid such errors by practice of begin..end etc. But suppose this did go in an actual design I'm trying to understand the implication on inferred logic. The else if always goes with the second if because the construct always has an immediate preceding if, but the else is not mandatory. — Rajesh S, May 29 '19 at 17:05
Doesn't else also always have an immediately preceding if? — The Photon, May 29 '19 at 17:06
Your second else if is also following an else if rather than a bare if. Do you know whether it goes with the inner or outer if? I still am not seeing why else and else if could be considered different. — The Photon, May 29 '19 at 17:08

dave_59 · Accepted Answer · 2019-05-29 23:16:43Z

4

You have to look at the BNF to understand how code is parsed. Indenting makes code easier to read, but is meaningless for the compiler

conditional_statement ::= // from A.6.6
          [ unique_priority ] if ( cond_predicate ) statement_or_null
          { else if ( cond_predicate ) statement_or_null }
          [ else statement_or_null ]

And a begin/end is considered a statement, as well as another nested conditional_statement. So your code is illegal because there is no statement_or_null after if(condition4) Adding a null ; would make the last else go with the last if.

Once you have a completely legal always block, a synthesis tool looks at the flow of variable references across all possible branches. If there's a possibility that a variable could be read without first being written, then is gets implemented as a latch. It's a bit more complicated than that; do read your synthesis tool manual.

edited May 29 '19 at 23:16

answered May 29 '19 at 18:49

dave_59

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\$\begingroup\$ Thanks for pointing that out. What does BNF stand for? \$\endgroup\$ – Rajesh S May 29 '19 at 20:41
\$\begingroup\$ @RajeshS BNF is Backus-Naur Form en.wikipedia.org/wiki/Backus%E2%80%93Naur_form \$\endgroup\$ – Greg May 29 '19 at 20:44
\$\begingroup\$ I missed out in representing it but I meant there would be single line logic after each of those if/else-if statements. \$\endgroup\$ – Rajesh S May 29 '19 at 20:44
\$\begingroup\$ @dave_59 could you please add a link to the BNF document for Verilog/SV as well? I got to go through a rudimentary document by a Google search but not the whole document. I think this was the missing link that can help me clear out such interpretation questions. The LRM doesn't help in these cases. \$\endgroup\$ – Rajesh S May 30 '19 at 4:42
\$\begingroup\$ It's in the LRM Annex A \$\endgroup\$ – dave_59 May 30 '19 at 16:01

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