This is the circuit with this values: $$\text{Logic gate of CMOS,VTH=2.5v,VCC=5v,Vz=3.3v,Vd=0.7,VBE=0.7}$$: enter image description here

The left side is working like a SR FF , and the right side Schmitt trigger comparator and I did calculate the VT1 and VT2 correct .

What is unclear for me is:

  • how does the PNP and NPN transistor work?
  • where is the base resistor?
  • what is the state of transistor Q1 and Q2(saturation, active, off )?

In addition, I'd like to know

  • how the capacitor charging and discarging and why? The target of the circuit is to output triangle wave what is unclear for me is why the capacitor will charge and discarge with constant current.
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    \$\begingroup\$ Very interesting circuit. Where did you find it? \$\endgroup\$ – AnalogKid May 29 '19 at 21:51

Figuring out that "middle part" of the circuit is easier when re-drawn slightly differently. Especially the diodes and zeners are better drawn showing the voltage going down through the chain.

The zener + diode in series are used when you don't want any current to flow when the current flows in the "non-zener" direction. That's what D1 and D4 do, they prevent current from flowing.

For example when bufout is high (+5V), D3 will "zener" and drop Vz, D4 will be in forward so drop 0.7 V, Q2 can then switch on. Current could flow through D2 in the direction of D1 however, D1 blocks that so no current flows into Q1.

When bufout is low (0V) then the reverse happens, D1 and D2 conduct and D4 will block the current through D3.

bufout is either +5 V or 0 V, the voltage drop across a zener + diode + Vbe of a transistor is fairly constant, the rest is dropped across R1 or R2.

A constant voltage across R1 + NPN like that behaves as a current source. Same for R2 and Q2. That means the capacitor C1 is charged (Q1) and discharged (Q2) with a somewhat constant current. It depends on the values of the emitter resistors, supply voltage and zener voltages what that current will be.

What will be the voltage across the capacitor if it is (dis)charged with a constant current?


simulate this circuit – Schematic created using CircuitLab

| improve this answer | |
  • \$\begingroup\$ Thanks, VT1=3.33v and VT2=1.66v so I guess the capacitor will charge to 3.33 and dis to 1.66, what happens in the middle of the process? there is no option that one of the transistor can be in saturation? or something else? why my lecturer said, "when there is no resistor in the base you can say IE=IC"(neglect IB), Why? @Bimpelrekkie \$\endgroup\$ – Knowledge May 29 '19 at 21:45
  • \$\begingroup\$ please help me d \$\endgroup\$ – Knowledge May 30 '19 at 11:09
  • \$\begingroup\$ what happens in the middle of the process? That's what is explained in my answer, you should ask your lecturer to explain this in more detail. He/she gets paid for that. \$\endgroup\$ – Bimpelrekkie May 30 '19 at 11:26
  • \$\begingroup\$ my questions was why IE=IC thats all \$\endgroup\$ – Knowledge May 30 '19 at 16:31
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    \$\begingroup\$ when there is no resistor in the base you can say IE=IC"(neglect IB) Again, ask your teacher to explain that, to me, having no base resistor isn't in any way related to assuming Ic = Ie. So in my opinion your teacher either doesn't understand this or isn't explaining it very well. Assuming Ic = Ie and thus ignoring Ib is just an assumption to help understand how the circuit works. But not having a base resistor isn't related to that, it is unclear to me why your teacher would say that. \$\endgroup\$ – Bimpelrekkie May 30 '19 at 21:32

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