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I have a question regarding the following circuit:

schematic

simulate this circuit – Schematic created using CircuitLab

This circuit gives 30V to the output when the clock input is HIGH, and gives near zero when the input is LOW. But how does this make that exactly? I have trouble in understanding how M1 can put nearly 0V when CLK is OFF.

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On basic level you can consider these FETs to be relays controlled at the gate. When M1's gate is held low the drain-source resistance is absurdly high and is effectively an open circuit. at that point you can see that the current flowing is 0A and the output is grounded.

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When CLK1 is high-
M3 conducts with Rds << R1, R2. Assuming it's negligble. V_G(M1) = 25V and V_S(M1) = 30V. So V_GS(M1) = -5V -> M1 conducts and OUT is high.

When CLK1 is low-
M3 doesn't conduct and so V_G(M1) = 30V. This gives V_GS(M1) = 0V -> M1 doesn't conduct and OUT is low.

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The low voltage you see at the output is not "provided" by M1.

When CLK1 is low, M3 is off, therefore the gate of M1 is driven to +30 V by R1. Since M1 Vgs is zero, M1 is off as well, and the output is driven low by R4.

You can prove this to yourself connecting a (very small) load to the output, you will see that when the input is high, the load will be driven "strongly", while when the input is low, the load will be driven "weakly". Try with a 1 uF cap and connect a scope to the circuit.

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